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ORCIDKaustav Banerjee
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- affiliation: University of California, Santa Barbara, CA, USA
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2020 – today
- 2023
[c54]Ankit Kumar, Arnab Pal, Kamyar Parto, Wei Cao, Kaustav Banerjee:
Exploration and Exploitation of Strain Engineering in 2D-FETs. DRC 2023: 1-2- 2020
- [j16]Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo
, Kaustav Banerjee:
Correction to "Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 277 (2020)
2010 – 2019
- 2013
- [j15]Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo, Kaustav Banerjee:
Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(7): 1045-1058 (2013) - [c53]Wei Cao, Jiahao Kang, Wei Liu, Yasin Khatami, Deblina Sarkar, Kaustav Banerjee:
2D electronics: Graphene and beyond. ESSDERC 2013: 37-44 - 2012
- [j14]Chuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee:
Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(11): 1698-1710 (2012) - 2010
- [j13]Hong Li, Chuan Xu, Kaustav Banerjee:
Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs. IEEE Des. Test Comput. 27(4): 20-31 (2010) - [j12]Navin Srivastava, Chuan Xu, Roberto Suaya, Kaustav Banerjee:
Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 849 (2010) - [j11]Hamed F. Dadgour, Kaustav Banerjee:
A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates. IEEE Trans. Very Large Scale Integr. Syst. 18(11): 1567-1577 (2010) - [c52]Hamed F. Dadgour, Muhammad Mustafa Hussain, Casey Smith, Kaustav Banerjee:
Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS. DAC 2010: 893-896 - [c51]Hamed F. Dadgour, Kaustav Banerjee:
Aging-resilient design of pipelined architectures using novel detection and correction circuits. DATE 2010: 244-249 - [c50]Navin Srivastava, Roberto Suaya, Kaustav Banerjee:
Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. DATE 2010: 459-464 - [c49]Seid Hadi Rasouli, Kazuhiko Endo, Kaustav Banerjee:
Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design. ICCAD 2010: 714-720 - [c48]Hamed F. Dadgour, Muhammad Mustafa Hussain, Kaustav Banerjee:
A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs. ISLPED 2010: 7-12
2000 – 2009
- 2009
- [j10]Hamed F. Dadgour, Kaustav Banerjee:
Hybrid NEMS-CMOS integrated circuits: A novel strategy for energy-efficient designs. IET Comput. Digit. Tech. 3(6): 593-608 (2009) - [j9]Navin Srivastava, Roberto Suaya, Kaustav Banerjee:
Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(7): 1047-1060 (2009) - [c47]Seid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee:
High-speed low-power FinFET based domino logic. ASP-DAC 2009: 829-834 - [c46]Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger:
CMOS vs Nano: comrades or rivals? FPGA 2009: 121-122 - [c45]Seid Hadi Rasouli, Kazuhiko Endo, Kaustav Banerjee:
Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization. ICCAD 2009: 505-512 - [c44]Chuan Xu, Lijun Jiang, Seshadri K. Kolluri, Barry J. Rubin, Alina Deutsch, Howard H. Smith, Kaustav Banerjee:
Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologies. ICCAD 2009: 658-665 - [c43]Kaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar, Seid Hadi Rasouli:
Graphene based transistors: physics, status and future perspectives. ISPD 2009: 65-66 - [c42]Kaustav Banerjee:
Graphene based nanomaterials for VLSI interconnect and energy-storage applications. SLIP 2009: 105-106 - 2008
- [j8]Sheng-Chih Lin, Kaustav Banerjee:
A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. 16(11): 1488-1498 (2008) - [c41]Chaitanya Kshirsagar, Mohamed N. El-Zeftawi, Kaustav Banerjee:
Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs. DAC 2008: 250-255 - [c40]Navin Srivastava, Roberto Suaya, Kaustav Banerjee:
High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. DATE 2008: 426-431 - [c39]Hamed F. Dadgour, Vivek De, Kaustav Banerjee:
Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. ICCAD 2008: 270-277 - 2007
- [j7]Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood:
3D Integration for Introspection. IEEE Micro 27(1): 77-83 (2007) - [c38]Hamed F. Dadgour, Kaustav Banerjee:
Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications. DAC 2007: 306-311 - [c37]Nikil D. Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha:
Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. VLSI Design 2007: 8 - 2006
- [c36]Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava:
Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. ASP-DAC 2006: 223-230 - [c35]Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood:
Introspective 3D chips. ASPLOS 2006: 264-273 - [c34]Kaustav Banerjee, Navin Srivastava:
Are carbon nanotubes the future of VLSI interconnections? DAC 2006: 809-814 - [c33]Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee:
A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. DAC 2006: 977-982 - [c32]Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee:
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. DAC 2006: 991-996 - [c31]Sheng-Chih Lin, Kaustav Banerjee:
An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management. ICCAD 2006: 568-574 - [c30]Rajiv V. Joshi, Kaustav Banerjee, André DeHon:
Tutorial 1: Emerging Technologies for VLSI Design. ISQED 2006: 4 - [c29]Kaustav Banerjee, Sungjun Im, Navin Srivastava:
Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections? Nano-Net 2006: 1-9 - 2005
- [j6]Amir H. Ajami, Kaustav Banerjee, Massoud Pedram:
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6): 849-861 (2005) - [j5]Man Lung Mui, Kaustav Banerjee, Amit Mehrotra:
Supply and power optimization in leakage-dominant technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9): 1362-1371 (2005) - [c28]Navin Srivastava, Kaustav Banerjee:
Performance analysis of carbon nanotube interconnects for VLSI applications. ICCAD 2005: 383-390 - [c27]Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee:
A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. ICCD 2005: 411-416 - [c26]Vineet Wason, Kaustav Banerjee:
A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations. ISLPED 2005: 131-136 - [c25]Navin Srivastava, Xiaoning Qi, Kaustav Banerjee:
Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits. ISQED 2005: 346-351 - [c24]Lech Józwiak, Kaustav Banerjee:
Plenary Session 2P. ISQED 2005: 461 - 2004
- [j4]Adil Koukab, Kaustav Banerjee, Michel J. Declercq:
Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6): 823-836 (2004) - [c23]Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee:
Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era. DAC 2004: 884-887 - [c22]Songqing Zhang, Vineet Wason, Kaustav Banerjee:
A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations. ISLPED 2004: 156-161 - [c21]Anirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, Kaustav Banerjee:
A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array. ISQED 2004: 259-264 - [c20]Man Lung Mui, Kaustav Banerjee, Amit Mehrotra:
Power Supply Optimization in sub-130 nm Leakage Dominant Technologies . ISQED 2004: 409-414 - 2003
- [c19]Sandeep K. Shukla, Ramesh Karri, Seth Copen Goldstein, Forrest Brewer, Kaustav Banerjee, Sankar Basu:
Nano, quantum, and molecular computing: are we ready for the validation and test challenges? HLDVT 2003: 3-7 - [c18]Santanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian M. Ionescu:
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits. ICCAD 2003: 497-503 - 2002
- [j3]Kaustav Banerjee, Amit Mehrotra:
Analysis of on-chip inductance effects for distributed RLC interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8): 904-915 (2002) - [c17]Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier:
Few electron devices: towards hybrid CMOS-SET integrated circuits. DAC 2002: 88-93 - [c16]Adil Koukab, Kaustav Banerjee, Michel J. Declercq:
Analysis and optimization of substrate noise coupling in single-chip RF transceiver design. ICCAD 2002: 309-316 - [c15]Santanu Mahapatra, Adrian M. Ionescu, Kaustav Banerjee, Michel J. Declercq:
A SET quantizer circuit aiming at digital communication system. ISCAS (5) 2002: 860-863 - [c14]Kaustav Banerjee, Amit Mehrotra:
Inductance Aware Interconnect Scaling. ISQED 2002: 43-47 - [c13]Adrian M. Ionescu, V. Pott, R. Fritschi, Kaustav Banerjee, Michel J. Declercq, Philippe Renaud, C. Hibert, Philippe Flückiger, G. A. Racine:
Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture. ISQED 2002: 496-501 - 2001
- [j2]Jeffery A. Davis, Raguraman Venkatesan, Alan Kaloyeros, Michael Beylansky, Shukri J. Souri, Kaustav Banerjee, Krishna C. Saraswat, Arifur Rahman, Rafael Reif, James D. Meindl:
Interconnect limits on gigascale integration (GSI) in the 21st century. Proc. IEEE 89(3): 305-324 (2001) - [j1]Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, Krishna C. Saraswat:
3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proc. IEEE 89(5): 602-633 (2001) - [c12]Amir H. Ajami, Massoud Pedram, Kaustav Banerjee:
Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs. CICC 2001: 233-236 - [c11]Yi-Chang Lu, Kaustav Banerjee, Mustafa Celik, Robert W. Dutton:
A fast analytical technique for estimating the bounds of on-chip clock wire inductance. CICC 2001: 241-244 - [c10]Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, Lukas P. P. P. van Ginneken:
Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs. DAC 2001: 567-572 - [c9]Kaustav Banerjee, Amit Mehrotra:
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects. DAC 2001: 798-803 - [c8]Amir H. Ajami, Kaustav Banerjee, Massoud Pedram:
Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion. ICCAD 2001: 44-48 - [c7]Kaustav Banerjee, Amit Mehrotra:
Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets. ICCAD 2001: 158-164 - [c6]TingYen Chiang, Kaustav Banerjee, Krishna Saraswat:
Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects. ICCAD 2001: 165- - [c5]Kaustav Banerjee, Massoud Pedram, Amir H. Ajami:
Analysis and optimization of thermal issues in high-performance VLSI. ISPD 2001: 230-237 - [c4]Choshu Ito, Kaustav Banerjee, Robert W. Dutton:
Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications. ISQED 2001: 117-122 - 2000
- [c3]Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, Krishna Saraswat:
Multiple Si layer ICs: motivation, performance analysis, and design implications. DAC 2000: 213-220 - [c2]Krishna Saraswat, Shukri J. Souri, Kaustav Banerjee, Pawan Kapur:
Performance analysis and technology of 3-D ICs. SLIP 2000: 85-90
1990 – 1999
- 1999
- [c1]Kaustav Banerjee, Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli, Chenming Hu:
On Thermal Effects in Deep Sub-Micron VLSI Interconnects. DAC 1999: 885-891
Coauthor Index
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