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dblp: Victor M. van Santen https://dblp.org/pid/154/2994.html dblp person page RSS feed Wed, 02 Oct 2024 21:39:08 +0200 en-US daily 1 released under the CC0 1.0 license dblp@dagstuhl.de (dblp team) dblp@dagstuhl.de (dblp team) Computers/Computer_Science/Publications/Bibliographies http://www.rssboard.org/rss-specification https://dblp.org/img/logo.144x51.pngdblp: Victor M. van Santenhttps://dblp.org/pid/154/2994.html14451 Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability.https://doi.org/10.1109/TCSI.2024.3397460, , , , :
Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3269-3281 ()]]>https://dblp.org/rec/journals/tcasI/MohamedSASA24Mon, 01 Jul 2024 01:00:00 +0200 Machine Learning Unleashes Aging and Self-Heating Effects: From Transistors to Full Processor (Invited Paper).https://doi.org/10.1109/IRPS48228.2024.10529386, , , :
Machine Learning Unleashes Aging and Self-Heating Effects: From Transistors to Full Processor (Invited Paper). IRPS : 1-8]]>https://dblp.org/rec/conf/irps/AmrouchSDK24Mon, 01 Jan 2024 00:00:00 +0100 Technology Mapping for Cryogenic CMOS Circuits.https://doi.org/10.1109/ISVLSI61997.2024.00057, , , , , , , , :
Technology Mapping for Cryogenic CMOS Circuits. ISVLSI : 272-277]]>https://dblp.org/rec/conf/isvlsi/HienWSKPPCAW24Mon, 01 Jan 2024 00:00:00 +0100 Degradation Models and Optimizations for CMOS Circuits.https://publikationen.bibliothek.kit.edu/1000158506:
Degradation Models and Optimizations for CMOS Circuits. Karlsruhe University, Germany, ]]>https://dblp.org/rec/phd/basesearch/Santen23Sun, 01 Jan 2023 00:00:00 +0100 Massively Parallel Circuit Setup in GPU-SPICE.https://doi.org/10.1109/TC.2020.3032343, , , :
Massively Parallel Circuit Setup in GPU-SPICE. IEEE Trans. Computers 72(8): 2127-2138 ()]]>https://dblp.org/rec/journals/tc/SantenDHA23Tue, 01 Aug 2023 01:00:00 +0200 Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K.https://doi.org/10.1109/TCSI.2023.3278351, , , , , :
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K. IEEE Trans. Circuits Syst. I Regul. Pap. 70(8): 3089-3102 ()]]>https://dblp.org/rec/journals/tcasI/PariharSTPCA23Sun, 01 Jan 2023 00:00:00 +0100 Performance and Energy Studies on NC-FinFET Cache-Based Systems With FN-McPAT.https://doi.org/10.1109/TVLSI.2023.3285105, , , , :
Performance and Energy Studies on NC-FinFET Cache-Based Systems With FN-McPAT. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1280-1293 ()]]>https://dblp.org/rec/journals/tvlsi/RavipatiSSAP23Fri, 01 Sep 2023 01:00:00 +0200 Design Automation for Cryogenic CMOS Circuits.https://doi.org/10.1109/DAC56929.2023.10247824, , , , , , , :
Design Automation for Cryogenic CMOS Circuits. DAC : 1-6]]>https://dblp.org/rec/conf/dac/SantenWKPPCWA23Sun, 01 Jan 2023 00:00:00 +0100 Challenges in Machine Learning Techniques to Estimate Reliability from Transistors to Circuits.https://doi.org/10.1109/DFT59622.2023.10313528, , , :
Challenges in Machine Learning Techniques to Estimate Reliability from Transistors to Circuits. DFT : 1-6]]>https://dblp.org/rec/conf/dft/SantenKGA23Sun, 01 Jan 2023 00:00:00 +0100 Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths.https://doi.org/10.1109/IRPS48203.2023.10117751, , , , , :
Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths. IRPS : 1-6]]>https://dblp.org/rec/conf/irps/SantenGNCRA23Sun, 01 Jan 2023 00:00:00 +0100 On the Reliability of FeFET On-Chip Memory.https://doi.org/10.1109/TC.2021.3066899, , , :
On the Reliability of FeFET On-Chip Memory. IEEE Trans. Computers 71(4): 947-958 ()]]>https://dblp.org/rec/journals/tc/GensslerSHA22Sat, 01 Jan 2022 00:00:00 +0100 FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies.https://doi.org/10.1109/TVLSI.2021.3123112, , , , , :
FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies. IEEE Trans. Very Large Scale Integr. Syst. 30(3): 339-352 ()]]>https://dblp.org/rec/journals/tvlsi/RavipatiKSHPA22Sat, 01 Jan 2022 00:00:00 +0100 Minimizing Excess Timing Guard Banding Under Transistor Self-Heating Through Biasing at Zero-Temperature Coefficient.https://doi.org/10.1109/ACCESS.2021.3057900, , , , :
Minimizing Excess Timing Guard Banding Under Transistor Self-Heating Through Biasing at Zero-Temperature Coefficient. IEEE Access 9: 30687-30697 ()]]>https://dblp.org/rec/journals/access/SalaminSRHA21Fri, 01 Jan 2021 00:00:00 +0100 Self-Heating Effects from Transistors to Gates.https://doi.org/10.1109/VLSI-DAT52063.2021.9427356, , :
Self-Heating Effects from Transistors to Gates. VLSI-DAT : 1-4]]>https://dblp.org/rec/conf/vlsi-dat/SantenSA21Fri, 01 Jan 2021 00:00:00 +0100 Special Session: Machine Learning for Semiconductor Test and Reliability.https://doi.org/10.1109/VTS50974.2021.9441052, , , , , , , , , :
Special Session: Machine Learning for Semiconductor Test and Reliability. VTS : 1-11]]>https://dblp.org/rec/conf/vts/AmrouchCJKKKPST21Fri, 01 Jan 2021 00:00:00 +0100 Reliability-Driven Voltage Optimization for NCFET-based SRAM Memory Banks.https://doi.org/10.1109/VTS50974.2021.9441053, , , , :
Reliability-Driven Voltage Optimization for NCFET-based SRAM Memory Banks. VTS : 1-7]]>https://dblp.org/rec/conf/vts/SantenTCHA21Fri, 01 Jan 2021 00:00:00 +0100 On the Workload Dependence of Self-Heating in FinFET Circuits.https://doi.org/10.1109/TCSII.2019.2959700, , , :
On the Workload Dependence of Self-Heating in FinFET Circuits. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1949-1953 ()]]>https://dblp.org/rec/journals/tcas/SantenAKH20Wed, 01 Jan 2020 00:00:00 +0100 Impact of Self-Heating on Performance, Power and Reliability in FinFET Technology.https://doi.org/10.1109/ASP-DAC47756.2020.9045582, , , , , :
Impact of Self-Heating on Performance, Power and Reliability in FinFET Technology. ASP-DAC : 68-73]]>https://dblp.org/rec/conf/aspdac/SantenGPTHA20Wed, 01 Jan 2020 00:00:00 +0100 NCFET to Rescue Technology Scaling: Opportunities and Challenges.https://doi.org/10.1109/ASP-DAC47756.2020.9045415, , , , :
NCFET to Rescue Technology Scaling: Opportunities and Challenges. ASP-DAC : 637-644]]>https://dblp.org/rec/conf/aspdac/AmrouchSPCH20Wed, 01 Jan 2020 00:00:00 +0100 Modeling Emerging Technologies using Machine Learning: Challenges and Opportunities.https://doi.org/10.1145/3400302.3415770, , , , :
Modeling Emerging Technologies using Machine Learning: Challenges and Opportunities. ICCAD : 15:1-15:9]]>https://dblp.org/rec/conf/iccad/KlemmePSHA20Wed, 01 Jan 2020 00:00:00 +0100 BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array - including Sense Amplifiers and Write Drivers - under Processor Activity.https://doi.org/10.1109/IRPS45951.2020.9128342, , , , , , , , :
BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array - including Sense Amplifiers and Write Drivers - under Processor Activity. IRPS : 1-7]]>https://dblp.org/rec/conf/irps/SantenTPGGSHMA20Wed, 01 Jan 2020 00:00:00 +0100 Modeling and Mitigating Time-Dependent Variability From the Physical Level to the Circuit Level.https://doi.org/10.1109/TCSI.2019.2898006, , :
Modeling and Mitigating Time-Dependent Variability From the Physical Level to the Circuit Level. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7): 2671-2684 ()]]>https://dblp.org/rec/journals/tcas/SantenAH19Tue, 01 Jan 2019 00:00:00 +0100 Modeling and Evaluating the Gate Length Dependence of BTI.https://doi.org/10.1109/TCSII.2018.2885850, , :
Modeling and Evaluating the Gate Length Dependence of BTI. IEEE Trans. Circuits Syst. II Express Briefs 66-II(9): 1527-1531 ()]]>https://dblp.org/rec/journals/tcas/SantenAH19aTue, 01 Jan 2019 00:00:00 +0100 Modeling the Interdependences Between Voltage Fluctuation and BTI Aging.https://doi.org/10.1109/TVLSI.2019.2899890, , , , , :
Modeling the Interdependences Between Voltage Fluctuation and BTI Aging. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1652-1665 ()]]>https://dblp.org/rec/journals/tvlsi/SalaminSAPMH19Tue, 01 Jan 2019 00:00:00 +0100 Reliability Challenges with Self-Heating and Aging in FinFET Technology.https://doi.org/10.1109/IOLTS.2019.8854405, , , , , , :
Reliability Challenges with Self-Heating and Aging in FinFET Technology. IOLTS : 68-71]]>https://dblp.org/rec/conf/iolts/AmrouchSPKSTH19Tue, 01 Jan 2019 00:00:00 +0100 Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV.https://doi.org/10.1109/TCSI.2017.2717790, , , , :
Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 293-306 ()]]>https://dblp.org/rec/journals/tcas/SantenMANH18Mon, 01 Jan 2018 00:00:00 +0100 Estimating and optimizing BTI aging effects: from physics to CAD.https://doi.org/10.1145/3240765.3243475, , :
Estimating and optimizing BTI aging effects: from physics to CAD. ICCAD : 125]]>https://dblp.org/rec/conf/iccad/AmrouchSH18Mon, 01 Jan 2018 00:00:00 +0100 Reliability Estimations of Large Circuits in Massively-Parallel GPU-SPICE.https://doi.org/10.1109/IOLTS.2018.8474096, , :
Reliability Estimations of Large Circuits in Massively-Parallel GPU-SPICE. IOLTS : 143-146]]>https://dblp.org/rec/conf/iolts/SantenAH18Mon, 01 Jan 2018 00:00:00 +0100 Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability.https://doi.org/10.1109/IRPS.2018.8353659, , , , , , , , , :
Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability. IRPS : 6-1]]>https://dblp.org/rec/conf/irps/SantenDAMRCRFHN18Mon, 01 Jan 2018 00:00:00 +0100 Interdependencies of Degradation Effects and Their Impact on Computing.https://doi.org/10.1109/MDAT.2016.2594180, , :
Interdependencies of Degradation Effects and Their Impact on Computing. IEEE Des. Test 34(3): 59-67 ()]]>https://dblp.org/rec/journals/dt/AmrouchSH17Sun, 01 Jan 2017 00:00:00 +0100 Designing guardbands for instantaneous aging effects.https://doi.org/10.1145/2897937.2898006, , , , :
Designing guardbands for instantaneous aging effects. DAC : 69:1-69:6]]>https://dblp.org/rec/conf/dac/SantenAMNH16Fri, 01 Jan 2016 00:00:00 +0100 Aging-aware voltage scaling.https://ieeexplore.ieee.org/document/7459378/, , , , :
Aging-aware voltage scaling. DATE : 576-581]]>https://dblp.org/rec/conf/date/SantenAPMH16Fri, 01 Jan 2016 00:00:00 +0100 Connecting the physical and application level towards grasping aging effects.https://doi.org/10.1109/IRPS.2015.7112711, , , , , , :
Connecting the physical and application level towards grasping aging effects. IRPS : 3]]>https://dblp.org/rec/conf/irps/AmrouchMSMRNH15Thu, 01 Jan 2015 00:00:00 +0100 Towards interdependencies of aging mechanisms.https://doi.org/10.1109/ICCAD.2014.7001394, , , , :
Towards interdependencies of aging mechanisms. ICCAD : 478-485]]>https://dblp.org/rec/conf/iccad/AmrouchSEWH14Wed, 01 Jan 2014 00:00:00 +0100