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Yong-Il Seo
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2010 – 2019
- 2013
- [j2]Bum Hwan Park, Yong-Il Seo, Sung-Pil Hong, Hag-Lae Rho:
Column Generation Approach to Line Planning with Various Halting Patterns - Application to the Korean High-Speed Railway. Asia Pac. J. Oper. Res. 30(4) (2013)
2000 – 2009
- 2009
- [j1]Ki-Tae Park, Myounggon Kang, Soonwook Hwang, Doo-Gon Kim, Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jae-hoon Jang, Hansoo Kim, Yeong-Taek Lee, Soon-Moon Jung, Changhyun Kim:
A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure. IEEE J. Solid State Circuits 44(1): 208-216 (2009) - 2008
- [c1]Ki-Tae Park, Doo-Gon Kim, Soonwook Hwang, Myounggon Kang, Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jae-hoon Jang, Hansoo Kim, Soon-Moon Jung, Yeong-Taek Lee, Changhyun Kim, Won-Seong Lee:
A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure. ISSCC 2008: 510-511
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last updated on 2024-04-24 23:14 CEST by the dblp team
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