default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID31st VLSI Design 2018: Pune, India
- 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, January 6-10, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-3692-3
Track 1A: Analog/RF - I
- Uma Mukund Kulkarni, Chetan D. Parikh, Subhajit Sen:
A Systematic Approach to Determining the Weights of the Capacitors in the DAC of a Non-binary Redundant SAR ADCs. 1-6 - Diego James, Abishek T. Kunnath, A. Purushothaman, Bibhudatta Sahoo:
Mitigating Aperture Error in Pipelined ADCs Without a Front-end Sample-and-Hold Amplfier. 7-12 - Biman Chattopadhyay, Sharath N. Bhat, Gopalkrishna Nayak, Ravi Mehta:
A 12.5Gbps Transmitter for Multi-standard SERDES in 40nm Low Leakage CMOS Process. 13-18 - Mahesh Kumar Adimulam, Amit Kapoor, Sreehari Veeramachaneni
, M. B. Srinivas:
An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications. 19-24
Track 1B: Power Management
- Sumanta Pyne:
Rescheduling of Power Gating Instructions for Reduction of In-rush Current. 25-30 - Alankar V. Umdekar, Arijit Nath, Shirshendu Das, Hemangee K. Kapoor:
Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors. 31-36 - Sudipa Mandal, Aritra Hazra, Pallab Dasgupta, Chunduri Rama Mohan:
Formal Methods for Coverage Analysis of Power Management Logic with Mixed-Signal Components. 37-42 - Sanjay Moulik, Arnab Sarkar, Hemangee K. Kapoor:
DPFair Scheduling with Slowdown and Suspension. 43-48
Track 1C: FPGA - I
- Anju P. Johnson, Junxiu Liu, Alan G. Millard, Shvan Karim, Andy M. Tyrrell, Jim Harkin, Jon Timmis, Liam McDaid, David M. Halliday:
Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs. 49-54 - Ravi Krishnan Unni, Vijayanand P., Y. Dilip:
FPGA Implementation of an Improved Watchdog Timer for Safety-Critical Applications. 55-60 - Nupur Jain, Mansi Singh, Biswajit Mishra:
Image Compression Using 2D-Discrete Wavelet Transform on a Light Weight Reconfigurable Hardware. 61-66 - Khyamling Parane, Basavaraj Talawar, Prabhu B. M. Prasad:
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs. 67-72
Track 2A: Security - I
- Vijaypal Singh Rathor, Bharat Garg, G. K. Sharma:
An Energy-Efficient Trusted FSM Design Technique to Thwart Fault Injection and Trojan Attacks. 73-78 - Ramakrishna Vaikuntapu, Lava Bhargava, Vineet Sahula:
Novel Variability Aware Path Selection for Self-Referencing Based Hardware Trojan Detection. 79-84 - Ujjwal Guin, Adit D. Singh, Mahabubul Alam, Janice Canedo, Anthony Skjellum:
A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things. 85-90 - Jonathan Cruz, Farimah Farahmandi, Alif Ahmed, Prabhat Mishra:
Hardware Trojan Detection Using ATPG and Model Checking. 91-96
Track 2B: Test
- Mudasir S. Kawoosa, Rajesh K. Mittal, Maheedhar Jalasuthram, Rubin A. Parekhji:
Towards Single Pin Scan for Extremely Low Pin Count Test. 97-102 - Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya:
Test-Time Reduction for Power-Aware 3D-SoC. 103-108 - Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri:
Identification of Faulty TSVs in 3D IC During Pre-Bond Testing. 109-114 - Avishek Choudhury, Biplab K. Sikdar:
Modeling & Analysis of Redundancy Based Fault Tolerance for Permanent Faults in Chip Multiprocessor Cache. 115-120
Track 2C: Devices and Emerging Technologies
- Oliver Keszöcze, Mohamed Ibrahim, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler:
Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips. 121-126 - Arpan Chakraborty, Piyali Datta, Rajat Kumar Pal:
Design Optimization at the Fluid-Level Synthesis for Safe and Low-Cost Droplet-Based Microfluidic Biochips. 127-132 - Manish Gupta, Abhinav Kranti:
Hysteresis Free sub-60 mV/dec Subthreshold Swing in Junctionless MOSFETs. 133-138 - Richa Chakravarty, Dipankar Saha, Santanu Mahapatra:
New Asymmetric Atomistic Model for the Analysis of Phase-Engineered MoS2-Gold Top Contact. 139-142
Track 3A: Security - II
- Ravikumar Selvam, Akhilesh Tyagi:
Power Side Channel Resistance of RNS Secure Logic. 143-148 - Bhuvana B. P., V. S. Kanchana Bhaaskaran:
Positive Feedback Symmetric Adiabatic Logic Against Differential Power Attack. 149-154 - Sarani Bhattacharya, Shivam Bhasin, Debdeep Mukhopadhyay:
Online Detection and Reactive Countermeasure for Leakage from BPU Using TVLA. 155-160 - James Thesing, Dhireesha Kudithipudi:
Secure Neural Circuits to Mitigate Correlation Power Analysis on SHA-3 Hash Function. 161-166
Track 3B: Oscillators
- Sucheth S. Kuncham, Manasa Gadiyar, Sushmitha Din K., Kiran Kumar Lad, Tonse Laxminidhi:
A Novel Zero Blind Zone Phase Frequency Detector for Fast Acquisition in Phase Locked Loops. 167-170 - R. R. Manikandan, Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale:
A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. 171-176 - Pragya Maheshwari, Sadhu Pavan Kumar, Mukesh Deharia, Nandakumar Nambath, Shalabh Gupta:
A Quadrature-Phase Voltage Controlled Oscillator for Offset Phase and Frequency Compensation. 177-180 - Vikas Rana:
CMOS Oscillator Having Stable Frequency with Process, Temperature and Voltage Variation. 181-185
Track 3C: FPGA - II
- Ayan Palchaudhuri, Anindya Sundar Dhar:
High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization. 186-191 - Nan Zheng, Pinaki Mazumder:
A Low-Power Circuit for Adaptive Dynamic Programming. 192-197 - Hari Shanker Gupta, Pranoy Datta, Maryam Shojaei Baghini, A. S. Kiran Kumar, Dinesh Kumar Sharma:
Low Power Configurable Readout Integrated Circuit for Infrared Detector. 198-203
Track 4A: Analog/RF - II
- Linga Reddy Cenkeramaddi:
Feedback Biasing Based Adjustable Gain Ultrasound Preamplifier for CMUTs in 45nm CMOS. 204-207 - Mannem Naga Sasikanth, Tarun Kanti Bhattacharyya:
A High Efficiency Body Injected Differential Power Amplifier at 2.4GHz for Low Power Applications. 208-213 - P. S. Veerendranath, M. H. Vasantha, Kumar Y. B. Nithin, Edoardo Bonizzoni:
A Novel Low Power G m-C Continuous-Time Analog Filter with Wide Tuning Range. 214-219 - Abhishek Srivastava, Maryam Shojaei Baghini:
0.36 nJ/bit MedRadio Band OOK Transmitter for Wearable Healthcare Applications. 220-225
Track 4B: Special Session - Power Management Integrated Circuits
- Qadeer Ahmad Khan, Seong Joong Kim, Pavan Kumar Hanumolu:
Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters - An Alternative to Conventional Analog and Digital Controllers. 226-231 - Punith R. Surkanti, Annajirao Garimella, Paul M. Furth:
Flipped Voltage Follower Based Low Dropout (LDO) Voltage Regulators: A Tutorial Overview. 232-237
Track 4C: Special Session - Energy Efficient and Reliable VLSI Systems
- Sudeep Pasricha:
Overcoming Energy and Reliability Challenges for IoT and Mobile Devices with Data Analytics. 238-243 - Shi Jin, Krishnendu Chakrabarty:
Data-Driven Resiliency Solutions for Boards and Systems. 244-249
Track 5A: Reliability and SRAMs
- Sai Aparna Aketi, Joycee Mekie, Hemal Shah:
Single-Error Hardened and Multiple-Error Tolerant Guarded Dual Modular Redundancy Technique. 250-255 - Ankur Shukla, Rahul M. Rao, James D. Warnock:
Impact of Device Aging on Early Mode Failures in Pulsed Latches. 256-260 - Ashish Kumar, G. S. Visweswaran:
A 0.6V Retention VMIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Adaptive Source Bias. 261-265 - M. Sultan M. Siddiqui, Sumit Srivastav, Dattatray Ramrao Wanjul, Manankumar Suthar, Sudhir Kumar:
A 7-Nm Dual Port 8T SRAM with Duplicated Inter-Port Write Data to Mitigate Write Disturbance. 266-270
Track 5B: VLSI Architecture
- M. Mohamed Asan Basiri, Sk. Noor Mahammad:
An Efficient VLSI Architecture for Convolution Based DWT Using MAC. 271-276 - Mahesh S. Murty, Rahul Shrestha:
Hardware-Efficient and Wide-Band Frequency-Domain Energy Detector for Cognitive-Radio Wireless Network. 277-282 - Mohd. Tasleem Khan, Shaik Rafi Ahamed:
Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter. 283-288 - Preyesh Dalmia, Vikas, Abhinav Parashar, Akshi Tomar, Neeta Pandey:
Novel High Speed Vedic Multiplier Proposal Incorporating Adder Based on Quaternary Signed Digit Number System. 289-294
Track 5C: Design Automation
- Ipsita Biswas Mahapatra, Utkarsh Agarwal, Chandrashekhar Azad, S. K. Nandy:
Design Space Exploration of an Execution-Driven Functional Simulation Methodology. 295-300 - Sneh Saurabh, Priyanka Mittal:
A Practical Methodology to Compress Technology Libraries Using Recursive Polynomial Representation. 301-306 - Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar:
CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems. 307-312 - Arindam Sinharay, Pranab Roy, Hafizur Rahaman:
Computing Fréchet Distance Metric Based L-Shape Tile Decomposition for E-Beam Lithography. 313-318
Track 6A: Analog/RF - II
- Kamal Chapagai, Pydi Bahubalindruni, Nishtha:
2nd Order Sallen Key Switched Capacitor LPF with N-type Transistors. 319-324 - Anjali Gopinath, Ravi Kumar Adusumalli, Rohit Ranganathan, Arya S.:
Pseudo-Continuous Output Switched-Capacitor Amplifier for Rail-to-Rail Current Sensing Application. 325-328 - Gregory Chang, Shovan Maity, Baibhab Chatterjee, Shreyas Sen:
Design Considerations of a Sub-50 Mu-W Receiver Front-end for Implantable Devices in MedRadio Band. 329-334 - Narendra Nath Ghosh, Prakash Kumar Lenka, SriHarsa Vardan G, Ashudeb Dutta:
A 0.6 mW 1.6 dB Noise Figure Inductorless Shunt Feedback Wideband LNA With Gm Enhancement and Current Reuse in 65 nm CMOS. 335-340
Track 6B: Regulators
- Nitin Bansal, Rahul Gupta:
An NMOS Low Drop-out Voltage Regulator with -17dB Wide-Band Power Supply Rejection for SerDes in 22FDX. 341-346 - Sowmya Sankaranarayanan, Kulkarni Chaitali Vinod, Aswanth Sreekumar, Tonse Laxminidhi, Vipul Singhal, Rajat Chauhan:
Single Inductor Dual Output Buck Converter for Low Power Applications and Its Stability Analysis. 347-352 - Nitin Bansal, Saurabh Kumar Singh, Hemant Shukla, Madhvi Sharma:
A 0.29ps FOM Fast Transient any Cap Stable LVR in 28FDSOI. 353-357 - Dharshak B. S., Rahul M. Rao:
A High Performance Gated Voltage Level Translator with Integrated Multiplexer. 358-361
Track 6C: Embedded Systems - I
- Mayuran Sivanesan, Anupam Chattopadhyay, Bajaj Ronak:
Accelerating Hash Computations Through Efficient Instruction-Set Customisation. 362-367 - Vinay B. Y. Kumar, Deval Shah, Mandar Datar, Sachin B. Patkar:
Lightweight Forth Programmable NoCs. 368-373 - John Jose, Abhijit Das:
An Adaptive Deflection Router with Dual Injection and Ejection Units for Mesh NoCs. 374-379 - Palash Das, Shivam Lakhotia, Prabodh Shetty, Hemangee K. Kapoor:
Towards Near Data Processing of Convolutional Neural Networks. 380-385
Track 7A: Security - III
- Amrita Roy Chowdhury, Parameswaran Ramanathan:
PPU: Privacy-Aware Purchasing Unit for Residential Customers in Smart Electric Grids. 386-391 - Jai Gopal Pandey, Tarun Goel, Abhijit Karmakar:
A High-Performance and Area-Efficient VLSI Architecture for the PRESENT Lightweight Cipher. 392-397 - Vishal Dey, Vikramkumar Pudi, Anupam Chattopadhyay, Yuval Elovici:
Security Vulnerabilities of Unmanned Aerial Vehicles and Countermeasures: An Experimental Study. 398-403
Track 7B: Verification and Validation
- Antonio Anastasio Bruto da Costa, Shriya Dharade, Sudipa Mandal, Pallab Dasgupta:
AMS-Miner: Mining AMS Assertions Using Interval Arithmetic. 404-409 - Ankit Jindal, Binod Kumar, Kanad Basu, Masahiro Fujita:
ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis. 410-415 - Xiaobang Liu, Ranga Vemuri:
Combined Inference and Satisfiability Based Methods for Complete Signal Restoration in Post-Silicon Validation. 416-421
Track 7C: Memory
- Md. Hasan Raza Ansari, Nupur Navlakha, Jyi-Tsong Lin, Abhinav Kranti:
Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access Memory. 422-427 - Mohammad Gh. Alfailakawi, Imtiaz Ahmad, Sarah Elghandour:
Energy-Efficient Dynamic Data Encoding for Multi-level STT-MRAM. 428-433 - Ashwani Kumar, Shubham Sahay, Manan Suri:
Switching-Time Dependent PUF Using STT-MRAM. 434-438 - Tarun Vatwani, Arko Dutt, Debjyoti Bhattacharjee, Anupam Chattopadhyay:
Floating Point Multiplication Mapping on ReRAM Based In-memory Computing Architecture. 439-444
Poster Papers
- Subhash J. Patel, Rajesh Amratlal Thakker:
Parasitic Aware Automatic Analog CMOS Circuit Design Environment Using ABC Algorithm. 445-446 - Vinay Kumar, Ravindra kumar Shrivatava, Madhav Mansukh Padaliya:
A Temperature Compensated Read Assist for Low Vmin and High Performance High Density 6T SRAM in FinFET Technology. 447-448 - Vulisi Narendra Kumar, Gayadhar Panda:
FPGA Implementation of Power Management Algorithm for Wind Energy Storage System with Kalman Filter MPPT Technique. 449-450 - Felipe Mendes, Tiago S. Curtinhas, Duarte Lopes de Oliveira, Higor A. Delsoto, Lester de Abreu Faria:
A Novel Tool for Synthesis by Direct Mapping of Asynchronous Circuits from Extended STG Specifications. 451-452 - Sourav Ghosh, Hafizur Rahaman, Chandan Giri:
Optimized Concurrent Testing of Digital Microfluidic Biochips. 453-454 - Rolf Arne Kjellby, Thor Eirik Johnsrud, Svein Erik Løtveit, Linga Reddy Cenkeramaddi, Mohamed Hamid, Baltasar Beferull-Lozano:
Self-Powered IoT Device for Indoor Applications. 455-456 - Sharma Priya, Sukarn Agarwal, Hemangee K. Kapoor:
Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets. 457-458 - Joycee Mekie, Prashansa Mukim, Kimaya Kale:
Impact of Variations on Synchronizer Performance: An Experimental Study. 459-460 - Sahu Sai Vikram, Vibha Panty, Mihir Mody, Madhura Purnaprajna:
TileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs. 461-462 - Krishnendu Guha, Sangeet Saha, Amlan Chakrabarti:
SHIRT (Self Healing Intelligent Real Time) Scheduling for Secure Embedded Task Processing. 463-464 - Preeti Ranjan Panda, Namita Sharma, Srikanth Kurra, Khushboo Anil Bhartia, Neeraj Kumar Singh:
Exploration of Loop Unroll Factors in High Level Synthesis. 465-466 - Sarit Chakraborty, Chandan Das, Susanta Chakraborty:
Securing Module-Less Synthesis on Cyberphysical Digital Microfluidic Biochips from Malicious Intrusions. 467-468 - Nagothu Karmel Kranthi, Abhishek Mishra, Adil Meersha, Mayank Shrivastava:
On the ESD Reliability Issues in Carbon Electronics: Graphene and Carbon Nano Tubes. 469-470
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-12 21:03 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
