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ORCID28th VLSI Design 2015: Bangalore, India
- 28th International Conference on VLSI Design, VLSID 2015, Bangalore, India, January 3-7, 2015. IEEE Computer Society 2015, ISBN 978-1-4799-6658-5
Tutorials, Special Sessions, and Invited Talks
- Bipin Rajendran, Udaya S. Ganguly, Manan Suri:
Tutorial T1: Neuromorphic Computing - Algorithms, Devices and Systems. 1-2 - Prabhat Mishra, Swarup Bhunia, Srivaths Ravi:
Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems. 3-5 - Jacob A. Abraham, Abhijit Chatterjee:
Tutorial T3: Error Resilient Real-Time Embedded Systems: Computing, Communications and Control. 6-7 - Nitin S. Kale:
Tutorial T4: MEMS: Design, Fabrication, and their Applications as Chemical and Biosensors. 8-9 - Nagesh Tamarapalli, Prashanth Vallur, Sachin Kulkarni:
Tutorial T5: High Performance Low Power Designs - Challenges and Best practices in Design, Verification and Test. 10-11 - Sudeb Dasgupta, Bulusu Anand:
Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges. 12-13 - Debdeep Mukhopadhyay, Rajat Subhra Chakraborty, Phuong Ha Nguyen, Durga Prasad Sahoo:
Tutorial T7: Physically Unclonable Function: A Promising Security Primitive for Internet of Things. 14-15 - Parmesh Ramanathan:
Tutorial T8: Scheduling Issues in Embedded Real-Time Systems. 16 - Sriram Ganesan:
Tutorial T9: Dealing with Startup Issues in Low Power Mixed Signal SoCs. 17-18 - Adit D. Singh:
Embedded Tutorial ET1: Better-than-Worst-Case Timing Designs. 19-20 - Wu-Tung Cheng, Sudhakar M. Reddy:
Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement. 21-23 - Virendra Gupta, Jayaraghavendran:
Invited Talk: IoT Protocols War and the Way Forward. 28
Session A1: Embedded Systems
- Jude Angelo Ambrose, Tuo Li, Daniel Murphy, Shivam Gargg, Nick Higgins, Sri Parameswaran
:
ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA. 29-34 - Pinalkumar Engineer, Rajbabu Velmurugan, Sachin B. Patkar:
Parameterizable FPGA Framework for Particle Filter Based Object Tracking in Video. 35-40 - Saurav Kumar Ghosh, Aritra Hazra, Soumyajit Dey:
RELSPEC: A Framework for Early Reliability Refinement of Embedded Applications. 41-46
Session A2: Embedded Systems
- Rehan Ahmed, Ayoosh Bansal, Bhuvana Kakunoori, Parameswaran Ramanathan, Kewal K. Saluja:
Thermal Extension of the Total Bandwidth Server. 47-52 - Rajit Karmakar, Santanu Chattopadhyay:
Thermal-Aware Test Data Compression Using Dictionary Based Coding. 53-58 - Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, Radi Husin Bin Ramlee, Mark Zwolinski:
CERI: Cost-Effective Routing Implementation Technique for Network-on-Chip. 59-64 - Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran:
Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors. 65-70
Session A4: Internet of Things and Products
- Anjan Kumar, Abhinav Dikshit, Bill Clark, Jeff Yan:
A Frequency Scan Scheme for PLL-Based Locking to High-Q MEMS Resonators. 71-74 - T. V. Prabhakar, Ujwal Mysore, Uday Saini, K. J. Vinoy, Bharadwaj Amruthur:
NFC for Pervasive Healthcare Monitoring. 75-80 - Gopinath Mahale, Hamsika Mahale, Arnav Goel, S. K. Nandy, S. Bhattacharya, Ranjani Narayan:
Hardware Solution for Real-Time Face Recognition. 81-86
Session A5: Product and Emerging Technologies
- Vignesh D. Kudva, Prashanth Nayak, Alok Rawat, Anjana G. Ry, K. R. Sheetal Kumar, Bharadwaj Amrutur, Mohan Kumar M. Sy:
Towards a Real-Time Campus-Scale Water Balance Monitoring System. 87-92 - Jude Baby George, Grace Mathew Abraham, Bharadwaj Amrutur, Sujit Kumar Sikdar:
Robot Navigation Using Neuro-electronic Hybrid Systems. 93-98 - Cory E. Merkel, Dhireesha Kudithipudi:
Comparison of Off-Chip Training Methods for Neuromemristive Systems. 99-104
Session A6: System Level Design
- Ramon Fernandes, Lucas Brahm, Thais Webber, Rodrigo Cataldo, Leticia B. Poehls, César A. M. Marcon:
OcNoC: Efficient One-Cycle Router Implementation for 3D Mesh Network-on-Chip. 105-110 - Dharanidhar Dang, Biplab Patra, Rabi N. Mahapatra, Martin Fiers:
Mode-Division-Multiplexed Photonic Router for High Performance Network-on-Chip. 111-116 - Gade Narayana Sri Harsha, Hemanta Kumar Mondal, Sujay Deb:
A Hardware and Thermal Analysis of DVFS in a Multi-core System with Hybrid WNoC Architecture. 117-122
Session A7: System Level Design
- Matthew Kennedy, Avinash Karanth Kodi:
Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-clockwise Optical Routing. 123-128 - Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead, Ankit More:
Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping. 129-134
Session A8: HPC
- Siddharth Nilakantan, Scott Lerner, Mark Hempstead, Baris Taskin:
Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation. 135-140 - Shirshendu Das, Hemangee K. Kapoor:
Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs. 141-146 - Santanu Sarma, Nikil D. Dutt:
Cross-Layer Exploration of Heterogeneous Multicore Processor Configurations. 147-152 - Farhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna C, Nalesh Sivanandan, Nandhini Gopalan, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. 153-158
Session B1: Design Verification
- Darvinder Singh, Isha Garg, Vineet Sachan, Prasanna Nalawar:
On-the-Fly Donut Formation in Compiled Memory. 159-163 - Abhishek Jain, Richa Gupta:
Scaling the UVM_REG Model towards Automation and Simplicity of Use. 164-169 - Jakia Sultana, Sajib Kumar Mitra, Ahsan Raja Chowdhury:
On the Analysis of Reversible Booth's Multiplier. 170-175
Session B2: Design Implementation
- M. Sultan M. Siddiqui, Shailendra Sharad, Yogendra Sharma, Amit Khanuja:
Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMs. 176-180 - Kedar Janardan Dhori, Vinay Kumar, Ashish Kumar:
A CMOS 90nm 50Mhz Supply Noise Tolerant High Density 8T-NAND ROM. 181-185 - Nitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala:
2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids. 186-191
Session B3: Design Verification
- Sumana Ghosh, Pallab Dasgupta:
Formal Methods for Pattern Based Reliability Analysis in Embedded Systems. 192-197 - Dushyant Juneja:
On Event Driven Modeling of Continuous Time Systems. 198-203
Session B4: Design Implementation
- Vinod Inipodu Murugan, Narayanan Mayandi, Arul Sendhil:
A Novel CKE-ODT-CSN Encoding Scheme in DDR Memory Interface. 204-208 - Naman Maheshwari, Zhixi Yang, Jie Han, Fabrizio Lombardi:
A Design Approach for Compressor Based Approximate Multipliers. 209-214 - Chandrashekar Dusa, Samiyuktha Kalalii, Pachamuthu Rajalakshmi, Omkeshwar Rao:
Integrated 16-Channel Transmit and Receive Beamforming ASIC for Ultrasound Imaging. 215-220
Session B5: Design Implementation
- Karthik Swaminathan, Jagadish Kotra, Huichu Liu, Jack Sampson, Mahmut T. Kandemir, Vijaykrishnan Narayanan:
Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures. 221-226 - Kaustav Guha, Sourav Saha, Ricardo Nigaglioni:
Exploring Scope of Power Reduction with Constrained Physical Synthesis. 227-231 - Pratik Dutta, Chandan Bandyopadhyay, Hafizur Rahaman:
All Optical Implementation of Mach-Zehnder Interferometer Based Reversible Sequential Counters. 232-237 - Nusrat Jahan Lisa, Hafiz Md. Hasan Babu:
Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming. 238-243
Session C1: Analog
- K. S. Rakshitdatta, Nagendra Krishnapura:
On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback. 244-248 - Imon Mondal, Nagendra Krishnapura:
Accurate Constant Transconductance Generation without Off-Chip Components. 249-253 - Saurabh Kumar Singh, Gautam Dey Kanungo:
Ultra-fast Cap-less LDO for Dual Lane USB in 28FDSOI. 254-259
Session C2: Analog
- Saurabh Kumar Singh, Nitin Bansal:
Any Capacitor Stable LVR Using Sub-unity Gain Positive Feedback Loop in 65nm CMOS. 260-264 - T. Rahul, Bibhudatta Sahoo, S. Arya, S. J. Parvathy, Veeresh Babu Vulligaddala:
A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application. 265-270 - Sivaramakrishna Rudrapati, Sharayu Jagtap, Mohammed Umar Shaikh, Shalabh Gupta:
A Wide Tuning Range LC Quadrature Phase Oscillator Employing Mode Switching. 271-275
Session C3: Devices and Circuits
- Radhika Gupta, Atul Bhargava, Rakeshshenoy Panemangalore:
Block-Level Electro-Migration Analysis (BEMA) for Safer Product Life. 276-281 - N. K. Kranthi, Radhakrishnan Sithanandam, Rama Komaragiri:
Recessed MOSFET in 28 nm FDSOI for Better Breakdown Characteristics. 282-285 - Debesh Bhatta, Suvadeep Banerjee, Abhijit Chatterjee:
A Noise Aware CML Latch Modelling for Large System Simulation. 286-291
Session C4: Devices and Circuits
- Sneh Lata Murotiya, Anu Gupta:
Design of High Speed Ternary Full Adder and Three-Input XOR Circuits Using CNTFETs. 292-297 - Yu Wang, Adit D. Singh:
An Efficient Transition Detector Exploiting Charge Sharing. 298-303 - Unsuk Heo, Xueqing Li, Huichu Liu, Sumeet Kumar Gupta, Suman Datta, Vijaykrishnan Narayanan:
A High-Efficiency Switched-Capacitance HTFET Charge Pump for Low-Input-Voltage Applications. 304-309
Session C6: Digital and FPGA
- Preeti Ranjan Panda, Vishal Patel, Praxal Shah, Namita Sharma, Vaidyanathan Srinivasan, Dipankar Sarma:
Power Optimization Techniques for DDR3 SDRAM. 310-315 - S. Dinesh Kumar, Sk. Noor Mahammad:
A Novel Ternary Content-Addressable Memory (TCAM) Design Using Reversible Logic. 316-320 - Guilherme Heck, Leandro S. Heck, Ajay Singhvi, Matheus T. Moreira, Peter A. Beerel, Ney Laert Vilar Calazans:
Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits. 321-326
Session C7: Digital and FPGA
- Pramod Kumar Meher, Basant Kumar Mohanty, M. N. S. Swamy:
Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters. 327-332 - Ankur Jaiswal, Bharat Garg, Vikas Kaushal, G. K. Sharma:
SPAA-Aware 2D Gaussian Smoothing Filter Design Using Efficient Approximation Techniques. 333-338
Session C8: Digital and FPGA
- Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan:
An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications. 339-344 - Gayathri R. Prabhu, Bibin Johnson, J. Sheeba Rani:
FPGA Based Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration. 345-350 - Sunil Dutt, Anshu Chauhan, Rahul Bhadoriya, Sukumar Nandi, Gaurav Trivedi:
A High-Performance Energy-Efficient Hybrid Redundant MAC for Error-Resilient Applications. 351-356 - Vikas Kaushal, Bharat Garg, Ankur Jaiswal, G. K. Sharma:
Energy Aware Computation Driven Approximate DCT Architecture for Image Processing. 357-362
Session D1: Test and Reliability
- V. R. Devanathan, Lakshmanan Balasubramanian, Rubin A. Parekhji:
New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation. 363-368 - Hadi Hajimiri, Kamran Rahmani, Prabhat Mishra:
Efficient Peak Power Estimation Using Probabilistic Cost-Benefit Analysis. 369-374 - Pradeep Nair, Nagarajan Viswanathan:
DFT Technique for Quick Characterization of Flash Offset in Pipeline ADCs. 375-380
Session D2: Test and Reliability
- Pavan Vithal Torvi, V. R. Devanathan, V. Kamakoti:
Framework for Selective Flip-Flop Replacement for Soft Error Mitigation. 381-386 - Bei Zhang, Vishwani D. Agrawal:
Diagnostic Tests for Pre-bond TSV Defects. 387-392 - Sindhu Gunasekar, Vishwani D. Agrawal:
Few Good Frequencies for Power-Constrained Test. 393-398
Session D3: Test and Reliability
- Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski:
Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. 399-404 - Felipe Lavratti, Letícia Maria Bolzani Poehls, Fabian Vargas, Andrea Calimera, Enrico Macii:
Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs. 405-410
Session D4: EDA
- Gaurav Narang, Pragya Sharma, Mansi Jain, Anuj Grover:
Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance. 411-416 - B. N. Bhramar Ray, Shankar Balachandran:
A Recursive Model for Smooth Approximation to Wirelength and Its Impact on Analytical Placement. 417-422 - Sameer Pawanekar, Gaurav Trivedi, Kalpesh Kapoor:
A Nonlinear Analytical Optimization Method for Standard Cell Placement of VLSI Circuits. 423-428
Session D5: EDA
- Antara Ain, Pallab Dasgupta:
Monitoring AMS Simulation: From Assertions to Features. 429-434 - Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler:
BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits. 435-440 - Sajib Kumar Mitra, Ahsan Raja Chowdhury:
Optimized Logarithmic Barrel Shifter in Reversible Logic Synthesis. 441-446
Session: Poster Session
- Partha Pratim Saha, Sumonto Saha, Tuhina Samanta:
Rectilinear Steiner Clock Tree Routing Technique with Buffer Insertion in Presence of Obstacles. 447-451 - Srinath R. Naidu:
Geometric Programming Formulation for Gate Sizing with Pipelining Constraints. 452-457 - Sai Praveen Kadiyala, Debasis Samanta:
On-the-Fly Mapping for Synthesizing Dynamic Domino Circuits. 458-463 - Arun Joseph, Anand Haridass, Charles Lefurgy, Spandana Rachamalla, Sreekanth Pai, Diyanesh Chinnakkonda, Vidushi Goyal:
FirmLeak: A Framework for Efficient and Accurate Runtime Estimation of Leakage Power by Firmware. 464-469 - Putluru Sravani, Madhav Rao:
Design of 3D Antennas for 24 GHz ISM Band Applications. 470-474 - Reenu James, John Jose, Jobin K. Antony:
Smart Port Allocation for Adaptive NoC Routers. 475-480 - Debjyoti Bhattacharjee, Ansuman Banerjee, Anupam Chattopadhyay:
EvoDeb: Debugging Evolving Hardware Designs. 481-486 - Spencer K. Millican, Kewal K. Saluja:
Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints. 487-492 - Aswin Srinivasa Rao, Karthik Subburaj:
A 300 KBPS 23.2 MHz Binary Frequency Shift Keying Transmitter for USB Power Line Communication in 180 nm BiCMOS. 493-498 - Suman Chatterjee, Vikram Singh Saun, Anand Arunachalam:
A Methodology for Placement of Regular and Structured Circuits. 499-504 - Mahnaz Mohammadi, Nitin Satpute, Rohit Ronge, Jayesh R. Chandiramani, S. K. Nandy, Aamir Raihan, Tanmay Verma, Ranjani Narayan, Sukumar Bhattacharya:
A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks. 505-510 - Hongwei Wang, Ziyuan Zhu, Jinglin Shi, Yongtao Su:
Sensitivity Analysis Based Predictive Modeling for MPSoC Performance and Energy Estimation. 511-516 - Anmol Gupta, Ashutosh Pal:
Accelerating SVM on Ultra Low Power ASIP for High Throughput Streaming Applications. 517-522 - Pravin Mane, Nishil Talati, Ameya Riswadkar, Bhavan Jasani, C. K. Ramesha:
Implementation of NOR Logic Based on Material Implication on CMOL FPGA Architecture. 523-528 - Kirmender Singh, A. B. Bhattacharyya:
Analysis of Second-Order Effect Components of Drain Conductance and Its Implication on Output Resistance of Wilson Current Mirror. 529-534 - Satya Narayan Shukla, Karan Kakwani, Amit Patra, Bipin Kumar Lahkar, Vivek Kumar Gupta, Alwar Jayakrishna, Puneet Vashisht, Induja Sreekanth:
Noninvasive Cuffless Blood Pressure Measurement by Vascular Transit Time. 535-540 - Deepak Baranwal, Digvijay Singh, Khanusiya Soyeb, Sidhartha Sankar Rout, Sujay Deb:
Reliability Enhancement of SoCs Based on Dynamic Memory Access Profiling in Conjunction with PVT Monitoring. 541-546 - Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Peeter Ellervee, Ahmed Hemani, Hannu Tenhunen, Juha Plosila:
DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs. 547-552
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