default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDICSAMOS 2010: Samos, Greece
- Fadi J. Kurdahi, Jarmo Takala:
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2010), Samos, Greece, July 19-22, 2010. IEEE 2010, ISBN 978-1-4244-7937-5
Keynotes
- Trevor N. Mudge:
Technologies for reducing power. - Tawfik Arabi:
VLSI challenges to more energy efficient devices.
Simulation and Modeling
- Igor Böhm, Björn Franke
, Nigel P. Topham:
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator. 1-10 - Peter van Stralen, Andy D. Pimentel:
A trace-based scenario database for high-level simulation of multimedia MP-SoCs. 11-19 - Alessandro Strano, Daniele Ludovici, Davide Bertozzi:
A library of dual-clock FIFOs for cost-effective and flexible MPSoC design. 20-27 - Taj Muhammad Khan, Daniel Gracia Pérez, Olivier Temam:
Transparent sampling. 28-36
Network Processing
- John McGlone, Roger F. Woods, Alan Marshall, Michaela Blott:
Design of a flexible high-speed FPGA-based flow monitor for next generation networks. 37-44 - Konstantin Septinus, Peter Pirsch, Holger Blume, Ulrich Mayer:
A fully programmable FSM-based Processing Engine for Gigabytes/s header parsing. 45-54 - Damon Fenacci, Björn Franke:
Empirical evaluation of data transformations for network infrastructure applications. 55-62 - Amin El Mrabti, Frédéric Rousseau, Frédéric Pétrot, Jérôme Martin, Romain Lemaire, Emmanuel Vaumorin:
Design environment for the support of configurable Network Interfaces in NoC-based platforms. 63-70
Image and Video Processing
- Muhammad Faisal Nadeem, Stephan Wong, Georgi Kuzmanov:
An efficient realization of forward integer transform in H.264/AVC intra-frame encoder. 71-78 - Tero Rintaluoma, Olli Silvén:
SIMD performance in software based mobile video coding. 79-85 - Tim Drijvers, Carlos A. Alba Pinto, Henk Corporaal, Bart Mesman, Gert-Jan van den Braak:
Fast Huffman decoding by exploiting data level parallelism. 86-92 - Christian Banz, Sebastian Hesselbarth, Holger Flatt, Holger Blume, Peter Pirsch:
Real-time stereo vision system using semi-global matching disparity estimation: Architecture and FPGA-implementation. 93-101
System-Level Design
- Sotirios Xydis, Alexandros Bartzas, Iraklis Anagnostopoulos, Dimitrios Soudris, Kiamal Z. Pekmestzi:
Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms. 102-109 - Oliver Arnold, Gerhard P. Fettweis:
Power aware heterogeneous MPSoC with dynamic task scheduling and increased data locality for multiple applications. 110-117 - Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubühr, Jürgen Teich:
A system-level synthesis approach from formal application models to generic bus-based MPSoCs. 118-125
Profiling and Analysis
- Christos Strydis, Dhara Dave, Georgi Gaydadjiev:
ImpBench revisited: An extended characterization of implant-processor benchmarks. 126-135 - Hojin Kee, Shuvra S. Bhattacharyya, Jacob Kornerup:
Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs. 136-143 - Amine Marref:
Compositional timing analysis. 144-151
MP-SoC Programming
- Samer Arandi, Paraskevas Evripidou:
Programming multi-core architectures using Data-Flow techniques. 152-161 - Erven Rohou, Andrea C. Ornstein, Marco Cornero:
CLI-based compilation flows for the C language. 162-169 - Unmesh D. Bordoloi, Huynh Phung Huynh, Tulika Mitra, Samarjit Chakraborty:
Design space exploration of instruction set customizable MPSoCs for multimedia applications. 170-177
Network-On-Chip Interconnects
- N. Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture. 178-184 - Radu Andrei Stefan, Jason de Windt, Kees Goossens:
On-chip network interfaces supporting automatic burst write creation, posted writes and read prefetch. 185-192 - Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Márcio Eduardo Kreutz:
Monitor-adapter coupling for NOC performance tuning. 193-199
Compiler Techniques
- Gert-Jan van den Braak, Bart Mesman, Henk Corporaal:
Compile-time GPU memory access optimizations. 200-207 - Xiaoyan Jia, Gerhard P. Fettweis:
Code generation for a novel STA architecture by using post-processing backend. 208-215 - Jens Huthmann, Peter Müller, Florian Stock, Dietmar Hildenbrand, Andreas Koch:
Accelerating high-level engineering computations by automatic compilation of Geometric Algebra to hardware accelerators. 216-222 - Pekka Jääskeläinen, Carlos S. de La Lama, Pablo Huerta, Jarmo Takala:
OpenCL-based design methodology for application-specific processors. 223-230
Micro-Architecture
- Anurag Negi, M. M. Waliullah, Per Stenström:
LV*: A low complexity lazy versioning HTM infrastructure. 231-240 - Catalin Bogdan Ciobanu, Georgi Kuzmanov, Georgi Gaydadjiev, Alex Ramírez:
A Polymorphic Register File for matrix operations. 241-249 - Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex Ramírez:
Interleaving granularity on high bandwidth memory architecture for CMPs. 250-257 - Per Karlström, Wenbiao Zhou, Dake Liu:
Automatic port and bus sizing in NoGap. 258-264
Design Space Exploration
- Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. 265-272 - Amir Yazdanbakhsh, Mehdi Kamal, Mostafa E. Salehi, Hamid Noori, Sied Mehdi Fakhraie:
Energy-aware design space exploration of registerfile for extensible processors. 273-281 - Marcela Zuluaga, Nigel P. Topham:
Exploring the unified design-space of custom-instruction selection and resource sharing. 282-291
Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR)
- John Glossner:
Special session on software defined radio (SDR) and Cognitive Radio (CR). 292 - Teemu Nylanden, Janne Janhunen, Olli Silvén, Markku J. Juntti:
A GPU implementation for two MIMO-OFDM detectors. 293-300 - Murugappan Senthilvelan, Javier Hormigo, Joon Hwa Chun, Mihai Sima, Daniel Iancu, Michael J. Schulte, John Glossner:
CORDIC-based LMMSE equalizer for Software Defined Radio. 301-308 - Peter Westermann, Hartmut Schröder:
On the scalability of SIMD processing for software defined radio algorithms. 309-317 - Jeroen Declerck, Praveen Raghavan, Frederik Naessens, Tom Vander Aa, Lieven Hollevoet, Antoine Dejonghe, Liesbet Van der Perre:
SDR platform for 802.11n and 3-GPP LTE. 318-323 - Sao-Jie Chen, Pao-Ann Hsiung, Chu Yu, Mao-Hsu Yen, Sakir Sezer, Michael J. Schulte, Yu Hen Hu:
ARAL-CR: An adaptive reasoning and learning cognitive radio platform. 324-331
Special Session on Multicore Architectures for Embedded Systems
- Luigi Carro, Stephan Wong:
Special session on multicore architectures for embedded systems. 332 - Chantal Ykman-Couvreur:
Exploration framework for Run-time Resource Management of embedded multi-core platforms. 333-340 - Michael A. Hicks, Michiel W. van Tol, Chris R. Jesshope:
Towards scalable I/O on a many-core architecture. 341-348 - Gabriel Falcão Paiva Fernandes, Leonel Sousa, Vítor Manuel Mendes da Silva:
Embedded multicore architectures for LDPC decoding. 349-356 - Diana Göhringer, Michael Hübner, Laure Hugot-Derville, Jürgen Becker:
Message Passing Interface support for the runtime adaptive multi-processor system-on-chip RAMPSoC. 357-364 - Fabio Arlati, Francesco Bruschi, Donatella Sciuto:
Designing and validating access policies to reconfigurable resources in Multiprocessor Systems on chip. 365-371 - Dmitry Nadezhkin, Todor P. Stefanov:
Identifying communication models in Process Networks derived from Weakly Dynamic Programs. 372-379
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-12 21:03 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
