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ORCIDISSCC 2016: San Francisco, CA, USA
- 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016. IEEE 2016, ISBN 978-1-4673-9466-6
- Laura Chizuko Fujino:
Reflections. 4 - Kevin Zhang:
Foreword: Silicon systems for the Internet of Everything. 5 - Anantha P. Chandrakasan, Kevin Zhang:
Session 1 overview: Plenary session. 6-7 - William M. Holt:
1.1 Moore's law: A path going forward. 8-13 - Sophie V. Vandebroek:
1.2 Three pillars enabling the Internet of Everything: Smart everyday objects, information-centric networks, and automated real-time insights. 14-20 - Seizo Onoe:
1.3 Evolution of 5G mobile technology toward 1 2020 and beyond. 23-28 - Lars Reger:
1.4 The road ahead for securely-connected cars. 29-33 - Ahmad Mirzaei, Hyunchol Shin:
Session 2 overview: RF frequency synthesis techniques. 34-35 - Yan Zhao, Zuow-Zun Chen, Gabriel Virbila, Yinuo Xu, Richard Al Hadi, Yanghyo Kim, Adrian Tang, Theodore Reck, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang
:
2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOS. 36-37 - Abhishek Agrawal, Arun Natarajan:
2.2 A scalable 28GHz coupled-PLL in 65nm CMOS with single-wire synchronization for large-scale 5G mm-wave arrays. 38-39 - Zhiqiang Huang, Bingwei Jiang, Lianming Li, Howard Cam Luong:
2.3 A 4.2µs-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL. 40-41 - Tino Copani, Claudio Asero, Matteo Colombo, Paolo Aliberti, Giuseppe Martino, Francesco Clerici:
2.4 A 2-to-16GHz BiCMOS ΔΣ fractional-N PLL synthesizer with integrated VCOs and frequency doubler for wireless backhaul applications. 42-43 - David Murphy, Hooman Darabi:
2.5 A complementary VCO for IoE that achieves a 195dBc/Hz FOM and flicker noise corner of 200kHz. 44-45 - Rouzbeh Kananizadeh, Omeed Momeni:
2.6 A 190.5GHz mode-switching VCO with 20.7% continuous tuning range and maximum power of -2.1dBm in 0.13µm BiCMOS. 46-47 - Jun Yin, Pui-In Mak, Franco Maloberti, Rui Paulo Martins:
2.7 A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise corner. 48-49 - Dongseok Shin, Sanjay Raman, Kwang-Jin Koh:
2.8 A mixed-mode injection frequency-locked loop for self-calibration of injection locking range and phase noise in 0.13µm CMOS. 50-51 - Sebastian Sievert, Ofir B. Degani, Assaf Ben Bassat, Rotem Banin, Ashoke Ravi, Bernd-Ulrich Klepser, Zdravko Boos, Doris Schmitt-Landsiedel:
2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOS. 52-54 - Hyeon-Min Bae, Ajith Amerasekera:
Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links. 54-55 - Sergey V. Rylov, Troy J. Beukema, Zeynep Toprak Deniz, Thomas Toifl, Yong Liu, Ankur Agrawal, Peter Buchmann, Alexander V. Rylyakov, Michael P. Beakes, Benjamin D. Parker, Mounir Meghelli:
3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. 56-57 - Delong Cui, Heng Zhang, Nick Huang, Ali Nazemi, Burak Çatli, Hyo-Gyuem Rhew, Bo Zhang, Afshin Momtaz, Jun Cao:
3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS. 58-59 - Takayasu Norimatsu, Takashi Kawamoto, Kenji Kogo, Naohiro Kohmu, Fumio Yuki, Norio Nakajima, Takashi Muto, Junya Nasu, Takemasa Komori, Hideki Koba, Tatsunori Usugi, Tomofumi Hokari, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, Masatoshi Tsuge, Takeo Yamashita, Masatoshi Hasegawa, Keiichi Higeta:
3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS. 60-61 - Karthik Gopalakrishnan, Alan Ren, Amber Tan, Arash Farhood, Arun Tiruvur, Belal Helal, Chang-Feng Loi, Chris Jiang, Halil Cirit, Irene Quek, Jamal Riani, James Gorecki, Jennifer Wu, Jorge Pernillo, Lawrence Tse, Michael Q. Le, Mohammad Ranjbar, Pui-Shan Wong, Pulkit Khandelwal, Rajesh Narayanan, Ravindran Mohanavelu, Sameer Herlekar, Sudeep Bhoja, Vlad Shvydun:
3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS. 62-63 - Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura:
3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS. 64-65 - Matteo Bassi, Francesco Radice, Melchiorre Bruccoleri, Simone Erba, Andrea Mazzanti:
3.6 A 45Gb/s PAM-4 transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS FDSOI. 66-67 - Yohan Frans, Scott McLeod, Hiva Hedayati, Mohamed Elzeftawi, Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang:
3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET. 68-70 - Mahesh Mehendale, Luke Shin:
Session 4 overview: Digital processors. 70-71 - Eyal Fayneh, Marcelo Yuffe, Ernest Knoll, Michael Zelikson, Muhammad Abozaed, Yair Talker, Ziv Shmuely, Saher Abu Rahme:
4.1 14nm 6th-generation Core processor SoC with low power consumption and improved performance. 72-73 - Aaron Grenat, Sriram Sundaram, Stephen Kosonocky, Ravinder Rachala, Sriram Sambamurthy, Steven Liepe, Miguel Rodriguez, Tom Burd, Adam Clark, Michael Austin, Samuel Naffziger:
4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management. 74-75 - Hugh Mair, Gordon Gammie, Alice Wang, Rolf Lagerquist, C. J. Chung, Sumanth Gururajarao, Ping Kao, Anand Rajagopalan, Anirban Saha, Amit Jain, Ericbill Wang, Shichin Ouyang, Huajun Wen, Achuta Thippana, HsinChen Chen, Syed Rahman, Minh Chau, Anshul Varma, Brian Flachs, Mark Peng, Alfred Tsai, Vincent Lin, Ue Fu, Wuan Kuo, Lee-Kee Yong, Clavin Peng, Leo Shieh, Jengding Wu, Uming Ko:
4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance. 76-77 - Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori:
4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems. 78-79 - Chikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji, Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita:
4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability. 80-81 - Michael Gautschi, Michael Schaffner, Frank K. Gürkaynak, Luca Benini:
4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster. 82-83 - Yongpan Liu, Zhibo Wang, Albert Lee, Fang Su, Chieh-Pu Lo, Zhe Yuan, Chien-Chen Lin, Qi Wei, Yu Wang, Ya-Chin King, Chrong Jung Lin, Pedram Khalili, Kang-Lung Wang, Meng-Fan Chang, Huazhong Yang:
4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic. 84-86 - Marco Berkhout, Tim Piessens:
Session 5 overview: Analog techniques. 86-87 - Vadim Ivanov, Munaf Shaik:
5.1 A 10MHz-bandwidth 4µs-large-signal-settling 6.5nV/√Hz-noise 2µV-offset chopper operational amplifier. 88-89 - Wen-Chieh Wang, Yu-Hsin Lin:
5.2 A 118dB-PSRR 0.00067%(-103.5dB) THD+N and 3.1W fully differential class-D audio amplifier with PWM common-mode control. 90-91 - Mikkel Hoyerby, Jorgen Kragh Jakobsen, Jesper Midtgaard, Thomas Holm Hansen, Allan Nogueras Nielsen, Hans Hasselby-Andersen:
5.3 A 2×70W monolithic five-level Class-D audio power amplifier. 92-93 - Frank M. Yaul, Anantha P. Chandrakasan:
5.4 A sub-µW 36nV/√Hz chopper amplifier for sensors using a noise-efficient inverter-based 0.2V-supply input stage. 94-95 - Hariprasad Chandrakumar, Dejan Markovic:
5.5 A 2µW 40mVpp linear-input-range chopper- stabilized bio-signal amplifier with boosted input impedance of 300MΩ and electrode-offset filtering. 96-97 - Marco Sautto, Fabio Quaglia, Giulio Ricotti, Andrea Mazzanti:
5.6 A 420µW 100GHz-GBW CMOS Programmable-Gain Amplifier leveraging the cross-coupled pair regeneration. 98-99 - Shunta Iguchi, Takayasu Sakurai, Makoto Takamiya:
5.7 A 39.25MHz 278dB-FOM 19µW LDO-free stacked-amplifier crystal oscillator (SAXO) operating at I/O voltage. 100-101 - Tae-Kwang Jang, Myungjoon Choi, Seokhyeon Jeong, Suyoung Bang, Dennis Sylvester, David T. Blaauw:
5.8 A 4.7nW 13.8ppm/°C self-biased wakeup timer using a switched-resistor scheme. 102-103 - Danielle Griffith, James Murdock, Per Torstein Røine:
5.9 A 24MHz crystal oscillator with robust fast start-up using dithered injection. 104-105 - Junghyup Lee, Arup K. George, Minkyu Je:
5.10 A 1.4V 10.5MHz swing-boosted differential relaxation oscillator with 162.1dBc/Hz FOM and 9.86psrms period jitter in 0.18µm CMOS. 106-108 - Jun Deguchi, David Stoppa:
Session 6 overview: Image sensors. 108-109 - Kazuko Nishimura, Yoshihiro Sato, Junji Hirase, Ryota Sakaida, Masaaki Yanagida, Tokuhiko Tamaki, Masayuki Takase, Hidenari Kanehara, Masashi Murakami, Yasunori Inoue:
6.1 An over 120dB simultaneous-capture wide-dynamic-range 1.6e- ultra-low-reset-noise organic-photoconductive-film CMOS image sensor. 110-111 - Sanshiro Shishido, Yasuo Miyake, Yoshiaki Sato, Tokuhiko Tamaki, Naoki Shimasaki, Yoshihiro Sato, Masashi Murakami, Yasunori Inoue:
6.2 210ke- Saturation signal 3µm-pixel variable-sensitivity global-shutter organic photoconductive image sensor for motion capture. 112-113 - Jan Bogaerts, Raf Lafaille, Marc Borremans, Jia Guo, Bart Ceulemans, Guy Meynants, Navid Sarhangnejad, Gavril Arsinte, Victor Statescu, Sonja van der Groen:
6.3 105×65mm2 391Mpixel CMOS image sensor with >78dB dynamic range for airborne mapping applications. 114-115 - Hirofumi Totsuka, Toshiki Tsuboi, Takashi Muto, Daisuke Yoshida, Yasushi Matsuno, Masanobu Ohmura, Hidekazu Takahashi, Katsuhito Sakurai, Takeshi Ichikawa, Hiroshi Yuzurihara, Shunsuke Inoue:
6.4 An APS-H-Size 250Mpixel CMOS image sensor using column single-slope ADCs with dual-gain amplifiers. 116-117 - Matteo Perenzoni, Daniele Perenzoni, David Stoppa:
6.5 A 64×64-pixel digital silicon photomultiplier direct ToF sensor with 100Mphotons/s/pixel background rejection and imaging/altimeter mode with 0.14% precision up to 6km for spacecraft navigation and landing. 118-119 - Mitsuyoshi Mori, Yusuke Sakata, Manabu Usuda, Sejii Yamahira, Shigetaka Kasuga, Yutaka Hirose, Yoshihisa Kato, Tsuyoshi Tanaka:
6.6 A 1280×720 single-photon-detecting image sensor with 100dB dynamic range using a sensitivity-boosting technique. 120-121 - Kei Shiraishi, Yasuhiro Shinozuka, Tomonori Yamashita, Kazuhide Sugiura, Naoto Watanabe, Ryuta Okamoto, Tatsuji Ashitani, Masanori Furuta, Tetsuro Itakura:
6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA. 122-123 - Charles Chih-Min Liu, Manoj M. Mhala, Chin-Hao Chang, Honyih Tu, Po-Sheng Chou, Calvin Chao, Fu-Lung Hsueh:
6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias. 124-125 - Toshiki Arai, Toshio Yasue, Kazuya Kitamura, Hiroshi Shimamoto, Tomohiko Kosugi, Sung-Wook Jun, Satoshi Aoyama, Ming-Chieh Hsu, Yuichiro Yamashita, Hirofumi Sumi, Shoji Kawahito:
6.9 A 1.1µm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-to-digital converters. 126-128 - Sungdae Choi, Jin-Man Han:
Session 7 overview: Nonvolatile memory solutions. 128-129 - Dongku Kang, Woopyo Jeong, Chulbum Kim, Doo-Hyun Kim, Yong-Sung Cho, Kyung-Tae Kang, Jinho Ryu, Kyung-Min Kang, Sungyeon Lee, Wandong Kim, Hanjun Lee, Jaedoeg Yu, Nayoung Choi, Dong-Su Jang, Jeong-Don Ihm, Doo-Gon Kim, Young-Sun Min, Moosung Kim, Ansoo Park, Jae-Ick Son, In-Mo Kim, Pansuk Kwak, Bong-Kil Jung, Doosub Lee, Hyunggon Kim, Hyang-Ja Yang, Dae-Seok Byeon, Ki-Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi:
7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers. 130-131 - Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura:
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. 132-133 - Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew BrightSky, SangBum Kim, Hsiang-Lam Lung, Chung Lam:
7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications. 134-135 - Chien-Chen Lin, Jui-Yu Hung, Wen-Zhang Lin, Chieh-Pu Lo, Yen-Ning Chiang, Hsiang-Jen Tsai, Geng-Hau Yang, Ya-Chin King, Chrong Jung Lin, Tien-Fu Chen, Meng-Fan Chang:
7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell. 136-137 - Seungjae Lee, Jin-Yub Lee, Il-Han Park, Jong-Yeol Park, Sung-Won Yun, Minsu Kim, Jong-Hoon Lee, Min-Seok Kim, Kangbin Lee, Taeeun Kim, Byungkyu Cho, Dooho Cho, Sangbum Yun, Jung-No Im, Hyejin Yim, Kyung-Hwa Kang, Suchang Jeon, Sungkyu Jo, Yang-Lo Ahn, Sung-Min Joe, Suyong Kim, Deok-kyun Woo, Jiyoon Park, Hyun Wook Park, Youngmin Kim, Jonghoon Park, Yongsu Choi, Makoto Hirano, Jeong-Don Ihm, Byunghoon Jeong, Seon-Kyoo Lee, Moosung Kim, Hokil Lee, Sungwhan Seo, Hongsoo Jeon, Chan-ho Kim, Hyunggon Kim, Jintae Kim, Yongsik Yim, Hoosung Kim, Dae-Seok Byeon, Hyang-Ja Yang, Ki-Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi:
7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate. 138-139 - Hidenori Mitani, Ken Matsubara, Hiroshi Yoshida, Takashi Hashimoto, Hideaki Yamakoshi, Shinichiro Abe, Takashi Kono, Yasuhiko Taito, Takashi Ito, Takashi Krafuji, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi:
7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C. 140-141 - Tomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, Toru Tanzawa, Jason Guo, Takaaki Ichikawa, Erwin Yu, Satoru Tamada, Tetsuji Manabe, Jiro Kishimoto, Yoko Oikawa, Yasuhiro Takashima, Hidehiko Kuge, Midori Morooka, Ali Mohammadzadeh, Jong Kang, Jeff Tsai, Emanuele Sirizotti, Eric Lee, Luyen Vu, Yuxing Liu, Hoon Choi, Kwonsu Cheon, Daesik Song, Daniel Shin, Jung Hee Yun, Michele Piccardi, Kim-Fung Chan, Yogesh Luthra, Dheeraj Srinivasan, Srinivasarao Deshmukh, Kalyan Kavalipurapu, Dan Nguyen, Girolamo Gallo, Sumant Ramprasad, Michelle Luo, Qiang Tang, Michele Incarnati, Agostino Macerola, Luigi Pilolli, Luca De Santis, Massimo Rossini, Violante Moschiano, Giovanni Santin, Bernardino Tronca, Hyunseok Lee, Vipul Patel, Ted Pekny, Aaron Yip, Naveen Prabhu, Purval Sule, Trupti Bemalkhedkar, Kiranmayee Upadhyayula, Camila Jaramillo:
7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory. 142-144 - Eric Fluhr, Bing Sheu:
Session 8 overview: Low-power digital circuits. 144-145 - Pascal Vivet, Yvain Thonnart, Romain Lemaire, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Cristiano Santos, Fabien Clermidy, Séverine Cheramy, Frédéric Pétrot, Eric Flamand, Jean Michailos:
8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. 146-147 - Doyun Kim, Mingoo Seok:
8.2 Fully integrated low-drop-out regulator based on event-driven PI control. 148-149 - Yong-Jin Lee, Min-Yong Jung, Shashank Singh, Tae-Hwang Kong, Dae-Yong Kim, Kwang-Ho Kim, Sang-Ho Kim, Jae-Jin Park, Ho-Jin Park, Gyu-Hyeong Cho:
8.3 A 200mA digital low-drop-out regulator with coarse-fine dual loop in mobile application processors. 150-151 - Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. 152-153 - Wanyeong Jung, Junhua Gu, Paul D. Myers, Minseob Shim, Seokhyeon Jeong, Kaiyuan Yang, Myungjoon Choi, Zhiyoong Foo, Suyoung Bang, Sechang Oh, Dennis Sylvester, David T. Blaauw:
8.5 A 60%-efficiency 20nW-500µW tri-output fully integrated power management unit with environmental adaptation and load-proportional biasing for IoT systems. 154-155 - John M. Wilson, Matthew R. Fojtik, John W. Poulton, Xi Chen, Stephen G. Tell, Thomas H. Greer, C. Thomas Gray, William J. Dally:
8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring. 156-157 - Bohdan Karpinskyy, Yongki Lee, Yunhyeok Choi, Yongsoo Kim, Mijung Noh, Sanghyun Lee:
8.7 Physically unclonable function for secure key generation with a key error rate of 2E-38 in 45nm smart-card chips. 158-160 - Yiqun Zhang, Mahmood Khayatzadeh, Kaiyuan Yang, Mehdi Saligane, Nathaniel Ross Pinckney, Massimo Alioto, David T. Blaauw, Dennis Sylvester:
8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor. 160-162 - Ali Afsahi, Guang-Kaai Dehng:
Session 9 overview: High-performance wireless. 162-163 - Nikolaus Klemmer, S. Akhtar, V. Srinivasan, P. Litmanen, Himanshu Arora, Satish Uppathil, Scott Kaylor, A. Akour, V. Wang, M. Fares, F. Dulger, A. Frank, D. Ghosh, S. Madhavapeddi, H. Safiri, J. Mehta, A. Jain, H. Choo, E. Zhang, Charles K. Sestok, C. Fernando, Rajagopal K. A., S. Ramakrishnan, V. Sinari, V. Baireddy:
9.1 A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD 2×2 MIMO base-station transceiver SoC with 200MHz RF bandwidth. 164-165 - Linxiao Zhang, Arun Natarajan, Harish Krishnaswamy:
9.2 A scalable 0.1-to-1.7GHz spatio-spectral-filtering 4-element MIMO receiver array with spatial notch suppression enabling digital beamforming. 166-167 - Jianxun Zhu, Peter R. Kinget:
9.3 A very-low-noise frequency-translational quadrature-hybrid receiver for carrier aggregation. 168-169 - Renaldi Winoto, Ashkan Olyaei, Mohammad Hajirostam, Wai Lau, Xiang Gao, Arnab Mitra, Ovidiu Carnu, Philip Godoy, Luns Tee, Hao Li, Erdem Erdogan, Alden Wong, Qiang Zhu, Timothy Loo, Fan Zhang, Liwei Sheng, Donghong Cui, Anuranjan Jha, Xiang Li, Wanghua Wu, Kun-Seok Lee, Derek Cheung, Ka Wo Pang, Haisong Wang, Jiexi Liu, Xingliang Zhao, Daibashish Gangopadhyay, David Cousinard, Arvind Anumula Paramanandam, Xiaoang Li, Norman Liu, Weiwei Xu, Yuan Fang, Xiaoyue Wang, Randy Tsang, Li Lin:
9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation. 170-171 - Zhiming Deng, Eric Lu, Edris Rostami, Dai Sieh, Dimitris Papadopoulos, Bryan Huang, Ray Chen, Hua Wang, W. H. Hsu, C. H. Wu, Osama Shana'a:
9.5 A dual-band digital-WiFi 802.11a/b/g/n transmitter SoC with digital I/Q combining and diamond profile mapping for compact die area and improved efficiency in 40nm CMOS. 172-173 - Xiang Gao, Olivier Burg, Haisong Wang, Wanghua Wu, Cao-Thong Tu, Konstantinos Manetakis, Fan Zhang, Luns Tee, Mustafa Yayla, Sining Xiang, Randy Tsang, Li Lin:
9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS. 174-175 - Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. 176-177 - Jin Zhou, Negar Reiskarimian, Harish Krishnaswamy:
9.8 Receiver with integrated magnetic-free N-path-filter-based non-reciprocal circulator and baseband self-interference cancellation for full-duplex wireless. 178-180 - Jaeha Kim, Roberto Nonis:
Session 10 overview: Advanced wireline transceivers and PLLs. 180-181 - Amin Shokrollahi, Dario Albino Carnelli, John Fox, Klaas L. Hofstra, Brian Holden, Ali Hormati, Peter Hunt, Margaret Johnston, John Keay, Sergio Pesenti, Richard Simpson, David Stauffer, Andrew Stewart, Giuseppe Surace, Armin Tajalli, Omid Talebi Amiri, Anton Tschank, Roger Ulrich, Christoph Walter, Fabio Licciardello, Yohann Mogentale, Anant Singh:
10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS. 182-183 - Wei-Han Cho, Yilei Li, Yuan Du, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Sheau Jiung Lee, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang:
10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface. 184-185 - Hui Pan, Junhua Tan, Evelyn Wenting Wang, Jingguang Wang, Karthik Swaminathan, Ramalingam Pandarinathan, Ramesh Pasagadugula, VamshiKrishna Yakkala, Mostafa Hammad, Karim Abdelhalim, Kaijun Li, Su Cui, Jing Wang, Ahmad Chini, Mehmet Tazebay, Suresh Venkatesan, Derek Tam, Ichiro Fujimori, Kambiz Vakilian:
10.3 An analog front-end for 100BASE-T1 automotive Ethernet in 28nm CMOS. 186-187 - Takashi Masuda, Ryota Shinoda, Jeremy Chatwin, Jacob Wysocki, Koki Uchino, Yoshifumi Miyajima, Yosuke Ueno, Kenichi Maruko, Zhiwei Zhou, Hideyuki Matsumoto, Hideyuki Suzuki, Norio Shoji:
10.4 A 12Gb/s 0.9mW/Gb/s wide-bandwidth injection-type CDR in 28nm CMOS with reference-free frequency capture. 188-189 - Cheng-Ru Ho, Mike Shuo-Wei Chen:
10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS. 190-191 - Ahmed Elkholy, Ahmed Elmallah, Mohamed Elzeftawi, Ken Chang, Pavan Kumar Hanumolu:
10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS. 192-193 - Seojin Choi, Seyeon Yoo, Jaehyouk Choi:
10.7 A 185fsrms-integrated-jitter and -245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector. 194-195 - Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman:
10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs. 196-198 - Yong Ping Xu, Joseph Shor:
Session 11 overview: Sensors and displays. 198-199 - Meisam Heidarpour Roshan, Samira Zali Asl, Kimo Joo, Kamran Souri, Rajkumar Palwai, Lijun Will Chen, Sudhakar Pamarti, Joseph C. Doll, Nicholas Miller, Carl Arft, Sassan Tabatabaei, Carl Sechen, Aaron Partridge, Vinod Menon:
11.1 Dual-MEMS-resonator temperature-to-digital converter with 40 K resolution and FOM of 0.12pJK2. 200-201 - Hao-Yen Tang, Yipeng Lu, Fari Assaderagh, Mike Daneman, Xiaoyue Jiang, Martin Lim, Xi Li, Eldwin Jiaqiang Ng, Utkarsh Singhal, Julius M. Tsai, David A. Horsley, Bernhard E. Boser:
11.2 3D ultrasonic fingerprint sensor-on-a-chip. 202-203 - Junfeng Jiang, Kofi A. A. Makinwa:
11.3 A hybrid multipath CMOS magnetic sensor with 210µTrms resolution and 3MHz bandwidth for contactless current sensing. 204-205 - Ugur Sonmez, Fabio Sebastiano, Kofi A. A. Makinwa:
11.4 1650µm2 thermal-diffusivity sensors with inaccuracies down to ±0.75°C in 40nm CMOS. 206-207 - David Ruffieux, Franz-Xaver Pengg, Nicola Scolari, Frédéric Giroud, Daniel Séverac, Thanh Le, Silvio Dalla Piazza, Olivier Aubry:
11.5 A 3.2×1.5×0.8mm3 240nA 1.25-to-5.5V 32kHz-DTCXO RTC module with an overall accuracy of µ1ppm and an all-digital 0.1ppm compensation-resolution scheme at 1Hz. 208-209 - Jun-Eun Park, Jiheon Park, Young-Ha Hwang, Jonghyun Oh, Deog-Kyoon Jeong:
11.6 A 100-TRX-channel configurable 85-to-385Hz-frame-rate analog front-end for touch controller with highly enhanced noise immunity of 20Vpp. 210-211 - Jun-Suk Bang, Hyunsik Kim, Kye-Seok Yoon, Sang-Han Lee, Se-Hong Park, Ohjo Kwon, Choongsun Shin, Seonki Kim, Gyu-Hyeong Cho:
11.7 A load-aware pre-emphasis column driver with 27% settling-time reduction in ±18% panel-load RC delay variation for 240Hz UHD flat-panel displays. 212-213 - Behnam Behroozpour, Phillip A. M. Sandborn, Niels Quack, Tae Joon Seok, Yasuhiro Matsui, Ming C. Wu, Bernhard E. Boser:
11.8 Chip-scale electro-optical 3D FMCW lidar with 8µm ranging precision. 214-216 - Vadim Ivanov, Jaejin Park:
Session 12 overview: Efficient Power Conversion. 216-217 - Wanyeong Jung, Dennis Sylvester, David T. Blaauw:
12.1 A rational-conversion-ratio switched-capacitor DC-DC converter using negative-output feedback. 218-219 - Nicolas Butzen, Michiel Steyaert:
12.2 A 94.6%-efficiency fully integrated switched-capacitor DC-DC converter in baseline 40nm CMOS using scalable parasitic charge redistribution. 220-221 - Chen Kong Teh, Atsushi Suzuki:
12.3 A 2-output step-up/step-down switched-capacitor DC-DC converter with 95.8% peak efficiency and 0.85-to-3.6V input voltage range. 222-223 - Daniel Lutz, Peter Renz, Bernhard Wicht:
12.4 A 10mW fully integrated 2-to-13V-input buck-boost SC converter with 81.5% peak efficiency. 224-225 - Jing Xue, Hoi Lee:
12.5 A 2MHz 12-to-100V 90%-efficiency self-balancing ZVS three-level DC-DC regulator with constant-frequency AOT V2 control and 5ns ZVS turn-on delay. 226-227 - Szu-Yu Huang, Kuan-Yu Fang, Yi-Wei Huang, Shih-Hsiung Chien, Tai-Haur Kuo:
12.6 Capacitor-current-sensor calibration technique and application in a 4-phase buck converter with load-transient optimization. 228-229 - Hsiang-An Yang, Wen-Hau Yang, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai, Shin-Chi Lai:
12.7 A 96%-efficiency and 0.5%-current-cross-regulation single-inductor multiple floating-output LED driver with 24b color resolution. 230-231 - Junsik Kim, Shihong Park:
12.8 Synchronized floating current mirror for maximum LED utilization in multiple-string linear LED drivers. 232-233 - Loai G. Salem, John G. Louie, Patrick P. Mercier:
12.9 A flying-domain DC-DC converter powering a Cortex-M0 processor with 90.8% efficiency. 234-236 - Yuu Watanabe, Pierre Busson:
Session 13 overview: Wireless systems. 236-237 - Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son, Jaeha Kim:
13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications. 238-239 - Yong Wang, Kai Tang, Ying Zhang, Liheng Lou, Bo Chen, Supeng Liu, Lei Qiu, Yuanjin Zheng:
13.2 A Ku-band 260mW FMCW synthetic aperture radar TRX with 1.48GHz BW in 65nm CMOS for micro-UAVs. 240-241 - Korkut Kaan Tokgoz, Shotaro Maki, Seitaro Kawai, Noriaki Nagashima, Jun Emmei, Masato Dome, Hisashi Kato, Jian Pang, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Yuuki Seo, Kimsrun Lim, Shinji Sato, Ning Li, Kengo Nakata, Kenichi Okada, Akira Matsuzawa:
13.3 A 56Gb/s W-band CMOS wireless transceiver. 242-243 - Mohammad Sadegh Mehrjoo, James F. Buckwalter:
13.4 A microwave injection-locking outphasing modulator with 30dB dynamic range and 22% system efficiency in 45nm CMOS SOI. 244-245 - Giovanni Mangraviti, Khaled Khalaf, Qixian Shi, Kristof Vaesen, Davide Guermandi, Vito Giannini, Steven Brebels, Fortunato Frazzica, André Bourdoux, Charlotte Soens, Wim Van Thillo, Piet Wambacq:
13.5 A 4-antenna-path beamforming transceiver for 60GHz multi-Gb/s communication in 28nm CMOS. 246-247 - Rui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon, Shoutarou Maki, Bangan Liu, Yun Wang, Noriaki Nagashima, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. 248-249 - Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx:
13.7 A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise. 250-252 - Paul Liang, Marian Verhelst:
Session 14 overview: Next-generation processing. 252-253 - Seongwook Park, Sungpill Choi, Jinmook Lee, Minseo Kim, Junyoung Park, Hoi-Jun Yoo:
14.1 A 126.1mW real-time natural UI/UX processor with embedded deep-learning core for low-power smart glasses. 254-255 - Kyuho Jason Lee, Kyeongryeol Bong, Changhyeon Kim, Jaeeun Jang, Hyunki Kim, Jihee Lee, Kyoung-Rog Lee, Gyeonghoon Kim, Hoi-Jun Yoo:
14.2 A 502GOPS and 0.984mW dual-mode ADAS SoC with RNN-FIS engine for intention prediction in automotive black-box system. 256-257 - Youchang Kim, Dongjoo Shin, Jinsu Lee, Yongsu Lee, Hoi-Jun Yoo:
14.3 A 0.55V 1.1mW artificial-intelligence processor with PVT compensation for micro robots. 258-259 - Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Gregory K. Chen, Sudhir Satpathy, Steven Hsu, Amit Agarwal, Ram Krishnamurthy:
14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS. 260-261 - Yu-Hsin Chen, Tushar Krishna, Joel S. Emer, Vivienne Sze:
14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. 262-263 - Jaehyeong Sim, Jun-Seok Park, Minhye Kim, Dongmyung Bae, Yeongjae Choi, Lee-Sup Kim:
14.6 A 1.42TOPS/W deep convolutional neural network recognition processor for intelligent IoE systems. 264-265 - Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto:
14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. 266-268 - Venkatesh Srinivasan, Tai-Cheng Lee:
Session 15 overview: Oversampling data converters. 268-269 - Bo Wu, Shuang Zhu, Benwei Xu, Yun Chiu:
15.1 A 24.7mW 45MHz-BW 75.3dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOS. 270-271 - Lucien J. Breems, Muhammed Bolatkale, Hans Brekelmans, Shagun Bajoria, Jan Niehof, Robert Rutten, Bert Oude-Essink, Franco Fritschij, Jagdip Singh, Gerard Lassche:
15.2 A 2.2GHz continuous-time ΔΣ ADC with -102dBc THD and 25MHz BW. 272-273 - Blazej Nowacki, Nuno Paulino, João Goes:
15.3 A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ΔΣM. 274-275 - Sujith Billa, Amrith Sukumaran, Shanthi Pavan:
15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts. 276-277 - Yunzhi Dong, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Richard Schreier, Qingdong Meng, José B. Silva, Donald Paterson, Jeffrey C. Gealow:
15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS. 278-279 - Su-Hao Wu, Tsung-Kai Kao, Zwei-Mei Lee, Ping Chen, Jui-Yuan Tsai:
15.6 A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique. 280-281 - Burak Gonen, Fabio Sebastiano, Robert H. M. van Veldhoven, Kofi A. A. Makinwa:
15.7 A 1.65mW 0.16mm2 dynamic zoom-ADC with 107.5dB DR in 20kHz BW. 282-283 - Matthias Steiner, Nigel Greer:
15.8 A 22.3b 1kHz 12.7mW switched-capacitor ΔΣ modulator with stacked split-steering amplifiers. 284-286 - Pirooz Parvarandeh, Shuichi Nagai:
Session 16 overview: Innovations in circuits and systems enabled by novel technologies. 286-287 - Drew A. Hall, Jonathan S. Daniels, Bibiche M. Geuskens, Noureddine Tayebi, Grace M. Credo, David J. Liu, Handong Li, Kai Wu, Xing Su, Madoo Varma, Oguz H. Elibol:
16.1 A nanogap transducer array on 32nm CMOS for electrochemical DNA sequencing. 288-289 - Chiraag Juvekar, Hyung-Min Lee, Joyce Kwong, Anantha P. Chandrakasan:
16.2 A Keccak-based wireless authentication tag with per-query key update and power-glitch attack countermeasures. 290-291 - Nicola Massari, Leonardo Gasparini, Alessandro Tomasi, Alessio Meneghetti, Hesong Xu, Daniele Perenzoni, Guglielmo Morgari, David Stoppa:
16.3 A 16×16 pixels SPAD-based 128-Mb/s quantum random number generator with -74dB light rejection ratio and -6.7ppm/°C bias sensitivity on temperature. 292-293 - Tiffany Moy, Liechao Huang, Warren Rieutort-Louis, Sigurd Wagner, James C. Sturm, Naveen Verma:
16.4 A flexible EEG acquisition and biomarker extraction system based on thin-film electronics. 294-295 - Florian De Roose, Kris Myny, Soeren Steudel, Myriam Willigems, Steve Smout, Tim Piessens, Jan Genoe, Wim Dehaene:
16.5 A flexible thin-film pixel array with a charge-to-current gain of 59µA/pC and 0.33% nonlinearity and a cost effective readout circuit for large-area X-ray imaging. 296-297 - Kris Myny, Soeren Steudel:
16.6 Flexible thin-film NFC transponder chip exhibiting data rates compatible to ISO NFC standards using self-aligned metal-oxide TFTs. 298-299 - Pierpaolo Lombardo, Vincenzo Fiore, Egidio Ragonese, Giuseppe Palmisano:
16.7 A fully-integrated half-duplex data/power transfer system with up to 40Mb/s data rate, 23mW output power and on-chip 5kV galvanic isolation. 300-301 - Xugang Ke, Joseph Sankman, Minkyu Song, Pooya Forghani, Dongsheng Brian Ma:
16.8 A 3-to-40V 10-to-30MHz automotive-use GaN driver with active BST balancing and VSW dual-edge dead-time modulation achieving 8.3% efficiency improvement and 3.4ns constant propagation delay. 302-304 - Hugh Mair, Atsushi Kawasumi:
Session 17 overview: SRAM. 304-305 - Taejoong Song, Woojin Rim, Sunghyun Park, Yongho Kim, Jonghoon Jung, Giyong Yang, Sanghoon Baek, Jaeseung Choi, Bongjae Kwon, Yunwoo Lee, Sungbong Kim, Gyu-Hong Kim, Hyo-Sig Won, Ja-Hum Ku, Sunhom Steve Paak, E. S. Jung, Steve Sungho Park, Kinam Kim:
17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization. 306-307 - John Keane, Jaydeep Kulkarni, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang:
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology. 308-309 - Mahmood Khayatzadeh, Mehdi Saligane, Jingcheng Wang, Massimo Alioto, David T. Blaauw, Dennis Sylvester:
17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI. 310-312 - Chulwoo Kim, Martin Brox:
Session 18 overview: High-bandwidth DRAM. 312-313 - Hye-Yoon Joo, Seung-Jun Bae, Young-Soo Sohn, Young-Sik Kim, Kyung-Soo Ha, Min-Su Ahn, Young-Ju Kim, Yong-Jun Kim, Ju-Hwan Kim, Won-Jun Choi, Chang-Ho Shin, Soo Hwan Kim, Byeong-Cheol Kim, Seung-Bum Ko, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin:
18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution. 314-315 - Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Kyung-Woo Nam, Seouk-Kyu Choi, Jaewook Lee, Uksong Kang, Young-Soo Sohn, Jung-Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Gyo-Young Jin:
18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution. 316-317 - Jong-Chern Lee, Jihwan Kim, Kyung Whan Kim, Young Jun Ku, Dae Suk Kim, Chunseok Jeong, Tae Sik Yun, Hongjung Kim, Ho Sung Cho, Yeon Ok Kim, Jae-Hwan Kim, Jin Ho Kim, Sangmuk Oh, Hyun Sung Lee, Ki Hun Kwon, Dong Beom Lee, Young Jae Choi, Jeajin Lee, Hyeon Gon Kim, Jun Hyun Chun, Jonghoon Oh, Seok Hee Lee:
18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface. 318-319 - Young Jun Yoon, Byung Deuk Jeon, Byung Soo Kim, Ki Up Kim, Tae Yong Lee, Nohhyup Kwak, Woo-Yeol Shin, Na Yeon Kim, Yunseok Hong, Kyeong Pil Kang, Dong Yoon Ka, Seong Ju Lee, Yong Sun Kim, Young Kyu Noh, Jaehoon Kim, Dong Keum Kang, Ho Uk Song, Hyeon Gon Kim, Jonghoon Oh:
18.4 An 1.1V 68.2GB/s 8Gb Wide-IO2 DRAM with non-contact microbump I/O test scheme. 320-322 - John Maneatis, Kathy Wilcox:
Session 19 overview: Digital PLLs. 322-323 - Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori:
19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC. 324-325 - Somnath Kundu, Bongjin Kim, Chris H. Kim:
19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection. 326-327 - Hyunik Kim, Yongjo Kim, Taeik Kim, Hojin Park, SeongHwan Cho:
19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS. 328-329 - Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Amr Elshazly, Nasser A. Kurd:
19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS. 330-331 - Che-Wei Yeh, Cheng-En Hsieh, Shen-Iuan Liu:
19.5 A 3.2GHz digital phase-locked loop with background supply-noise cancellation. 332-333 - Fahim U. Rahman, Visvesh S. Sathe:
19.6 voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2V DVFS System. 334-335 - Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura:
19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC. 336-337 - Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu:
19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS. 338-340 - Harish Krishnaswamy, Jussi Ryynänen:
Session 20 overview: RF-to-THz transceiver techniques. 340-341 - Kosuke Katayama, Kyoya Takano, Shuhei Amakawa, Shinsuke Hara, Akifumi Kasamatsu, Koichi Mizuno, Kazuaki Takahashi, Takeshi Yoshida, Minoru Fujishima:
20.1 A 300GHz 40nm CMOS transmitter with 32-QAM 17.5Gb/s/ch capability over 6 channels. 342-343 - ChandraKanth Reddy Chappidi, Kaushik Sengupta:
20.2 A frequency-reconfigurable mm-Wave power amplifier with active-impedance synthesis in an asymmetrical non-isolated combiner. 344-345 - Yue Chao, Lianming Li, Howard Cam Luong:
20.3 An 86-to-94.3GHz transmitter with 15.3dBm output power and 9.6% efficiency in 65nm CMOS. 346-347 - Samuel Jameson, Eliezer Halpern, Eran Socher:
20.4 A 300GHz wirelessly locked 2×3 array radiating 5.4dBm with 5.1% DC-to-RF efficiency in 65nm CMOS. 348-349 - Zeshan Ahmad, Mark Lee, Kenneth K. O:
20.5 1.4THz, -13dBm-EIRP frequency multiplier chain using symmetric- and asymmetric-CV varactors in 65nm CMOS. 350-351 - Sherif Shakib, Hyun-Chul Park, Jeremy Dunworth, Vladimir Aparin, Kamran Entesari:
20.6 A 28GHz efficient linear power amplifier for 5G phased arrays in 28nm bulk CMOS. 352-353 - Ji-Seon Paek, Yong-Sik Youn, Jeong-Hyun Choi, Dong-Su Kim, Jun-Hee Jung, Young-Hwan Choo, Sung-Jun Lee, Seung-Chul Lee, Thomas Byunghak Cho, Inyup Kang:
20.7 An RF-PA supply modulator achieving 83% efficiency and -136dBm/Hz noise for LTE-40MHz and GSM 35dBm applications. 354-355 - Benjamin P. Hershberg, Barend van Liempd, Xiaoqiang Zhang, Piet Wambacq, Jan Craninckx:
20.8 A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexers. 356-357 - Tian Ya Liu, Antonio Liscidini:
20.9 A 1.92mW filtering transimpedance amplifier for RF current passive mixers. 358-359 - Marco Vigilante, Patrick Reynaert:
20.10 A 68.1-to-96.4GHz variable-gain low-noise amplifier in 28nm CMOS. 360-362 - Anton Bakker, Yuan Gao:
Session 21 overview: Harvesting and wireless power. 362-363 - Xiaosen Liu, Edgar Sánchez-Sinencio:
21.1 A single-cycle MPPT charge-pump energy harvester using a thyristor-based VCO without storage capacitor. 364-365 - Daniel A. Sanchez, Joachim Leicht, Eduardas Jodka, Elham Fazel, Yiannos Manoli:
21.2 A 4µW-to-1mW parallel-SSHI rectifier for piezoelectric energy harvesting of periodic and shock excitations with inductor sharing, cold start-up and up to 681% power extraction improvement. 366-367 - Yanfeng Lu, Suyi Yao, Bin Shao, Paul Brokaw:
21.3 A 200nA single-inductor dual-input-triple-output (DITO) converter with two-stage charging and process-limit cold-start voltage for photovoltaic and thermoelectric energy harvesting. 368-369 - Inhee Lee, Wootaek Lim, Alan Teran, Jamie Phillips, Dennis Sylvester, David T. Blaauw:
21.4 A >78%-efficient light harvester over 100-to-100klux with reconfigurable PV-cell network and MPPT circuit. 370-371 - Myungjoon Choi, Tae-Kwang Jang, Junwon Jeong, Seokhyeon Jeong, David T. Blaauw, Dennis Sylvester:
21.5 A current-mode wireless power receiver with optimal resonant cycle tracking for implantable systems. 372-373 - Jian Kang, Patrick Yin Chiang, Arun Natarajan:
21.6 A 1.2cm2 2.4GHz self-oscillating rectifier-antenna achieving -34.5dBm sensitivity for wirelessly powered sensors. 374-375 - Lin Cheng, Wing-Hung Ki, Tat-To Wong, Tak-Sang Yim, Chi-Ying Tsui:
21.7 A 6.78MHz 6W wireless power receiver with a 3-level 1× / ½ × / 0× reconfigurable resonant regulating rectifier. 376-377 - Jong Tae Hwang, Dong Su Lee, Jong Hoon Lee, Sung Min Park, Ki Woong Jin, Min Jung Ko, Hyun Ick Shin, Sang Oh Jeon, Dae Ho Kim, Joon Rhee:
21.8 An all-in-one (Qi, PMA and A4WP) 2.5W fully integrated wireless battery charger IC for wearable applications. 378-380 - Long Yan, Refet Firat Yazicioglu:
Session 22 overview: Systems and instruments for human-machine interfaces. 380-381 - Yi-Kai Lo, Chih-Wei Chang, Yen-Cheng Kuan, Stanislav Culaclii, Brian Kim, Kuanfu Chen, Parag Gad, V. Reggie Edgerton, Wentai Liu:
22.2 A 176-channel 0.5cm3 0.7g wireless implant for motor function recovery after spinal cord injury. 382-383 - Yongsu Lee, Hyeonwoo Lee, Jaeeun Jang, Jihee Lee, Minseo Kim, Jaehyuk Lee, Hyunki Kim, Kyoung-Rog Lee, Kwantae Kim, Hyunwoo Cho, Seunghyup Yoo, Hoi-Jun Yoo:
22.3 A 141µW sensor SoC on OLED/OPD substrate for SpO2/ExG monitoring sticker. 384-385 - Pamula Venkata Rajesh, Jose Manuel Valero-Sarmiento, Long Yan, Alper Bozkurt, Chris Van Hoof, Nick Van Helleputte, Refet Firat Yazicioglu, Marian Verhelst:
22.4 A 172µW compressive sampling photoplethysmographic readout with embedded direct heart-rate and variability extraction from compressively sampled data. 386-387 - Minhao Yang, Chen-Han Chien, Tobias Delbrück, Shih-Chii Liu:
22.5 A 0.5V 55µW 64×2-channel binaural silicon cochlea for event-driven stereo-audio sensing. 388-389 - Natalie Butz, Armin Taschwer, Yiannos Manoli, Matthias Kuhl:
22.6 A 22V compliant 56µW active charge balancer enabling 100% charge compensation even in monophasic and 36% amplitude correction in biphasic neural stimulators. 390-391 - Carolina Mora Lopez, Srinjoy Mitra, Jan Putzeys, Bogdan C. Raducanu, Marco Ballini, Alexandru Andrei, Simone Severi, Marleen Welkenhuysen, Chris Van Hoof, Silke Musa, Refet Firat Yazicioglu:
22.7 A 966-electrode neural probe with 384 configurable channels in 0.13µm SOI CMOS. 392-393 - Vijay Viswam, Jelena Dragas, Amir Shadmani, Yihui Chen, Alexander Stettler, Jan Mueller, Andreas Hierlemann:
22.8 Multi-functional microelectrode array system featuring 59, 760 electrodes, 2048 electrophysiology channels, impedance and neurotransmitter measurement units. 394-396 - Frank O'Mahony, Simone Erba:
Session 23 overview: Electrical and optical link innovations. 396-397 - Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu:
23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. 398-399 - Chintan Thakkar, Shreyas Sen, James E. Jaussi, Bryan Casper:
23.2 A 32Gb/s bidirectional 4-channel 4pJ/b capacitively coupled link in 14nm CMOS for proximity communication. 400-401 - Mohammad Hekmat, Sanquan Song, Nancy Jaffari, Sabarish Sankaranarayanan, Chaofeng Huang, Minghui Han, Gaurav Malhotra, Jalil Kamali, Amir Amirkhany, Wei Xiong:
23.3 A 6Gb/s 3-tap FFE transmitter and 5-tap DFE receiver in 65nm/0.18µm CMOS for next-generation 8K displays. 402-403 - Enrico Temporiti, Gabriele Minoia, Matteo Repossi, Daniele Baldi, Andrea Ghilioni, Francesco Svelto:
23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies. 404-405 - Ahmed Awny, Rajasekhar Nagulapalli, Daniel Micusik, Jan Hoffmann, Gunter Fischer, Dietmar Kissinger, Ahmet Cagri Ulusoy:
23.5 A dual 64Gbaud 10kΩ 5% THD linear differential transimpedance amplifier with automatic gain control in 0.13µm BiCMOS technology for optical fiber coherent receivers. 406-407 - Pier Andrea Francese, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Alessandro Cevrero, Hazar Yueksel, Ilter Oezkaya, Danny Luu, Thomas Toifl:
23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path. 408-409 - Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone:
23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs. 410-411 - Abishek Manian, Behzad Razavi:
23.8 A 40Gb/s 14mW CMOS wireline receiver. 412-414 - Antoine Dupret, Subhasish Mitra:
Session 24 overview: Ultra-efficient computing: Application-inspired and analog-assisted digital. 414-415 - Dongsuk Jeon, Nathan Ickes, Priyanka Raina, Hsueh-Cheng Wang, Daniela Rus, Anantha P. Chandrakasan:
24.1 A 0.6V 8mW 3D vision processor for a navigation device for the visually impaired. 416-417 - Edward H. Lee, S. Simon Wong:
24.2 A 2.5GHz 7.7TOPS/W switched-capacitor matrix multiplier with co-designed local memory in 40nm. 418-419 - Skylar Skrzyniarz, Laura Fick, Jinal Shah, Yejoong Kim, Dennis Sylvester, David T. Blaauw, David Fick, Michael B. Henry:
24.3 A 36.8 2b-TOPS/W self-calibrating GPS accelerator implemented using analog calculation in 65nm LP CMOS. 420-422 - Brian P. Ginsburg, Minoru Fujishima:
Session 25 overview: Mm-Wave and THz sensing. 422-423 - Janusz Grzyb, Bernd Heinemann, Ullrich R. Pfeiffer:
25.1 A fully integrated 0.55THz near-field sensor with a lateral resolution down to 8µm in 0.13µm SiGe BiCMOS. 424-425 - Qian Zhong, Wooyeol Choi, Christopher Miller, Rashaunda Henderson, Kenneth K. O:
25.2 A 210-to-305GHz CMOS receiver for rotational spectroscopy. 426-427 - Xue Wu, Kaushik Sengupta:
25.3 A 40-to-330GHz synthesizer-free THz spectroscope-on-chip exploiting electromagnetic scattering. 428-429 - A. J. Tang, Yangyho Kim, Qun Jane Gu:
25.4 A 0.43K-noise-equivalent-ΔT 100GHz dicke-free radiometer with 100% time efficiency in 65nm CMOS. 430-431 - Chen Jiang, Ali Mostajeran, Ruonan Han, Mohammad Emadi, Hani Sherry, Andreia Cathelin, Ehsan Afshari:
25.5 A 320GHz subharmonic-mixing coherent imager in 0.13µm SiGe BiCMOS. 432-434 - Kenichi Okada, Jan van Sinderen:
Session 26 overview: Wireless for IoE. 434-435 - Hidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura:
26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS. 436-437 - Dawei Ye, Ronan A. R. van der Zee, Bram Nauta:
26.2 An Ultra-Low-Power receiver using transmitted-reference and shifted limiters for in-band interference resilience. 438-439 - Ao Ba, Yao-Hong Liu, Johan H. C. van den Heuvel, Paul Mateman, Benjamin Busze, Jordy Gloudemans, Peter Vis, Johan Dijkhuis, Christian Bachmann, Guido Dolmans, Kathleen Philips, Harmke de Groot:
26.3 A 1.3nJ/b IEEE 802.11ah fully digital polar transmitter for IoE applications. 440-441 - Niall Kearney, Charley Billon, Michael Deeney, Eric Evans, Kalim Khan, Hongxing Li, Siwen Liang, Kenneth Mulvaney, Keith A. O'Donoghue, Shane O'Mahony, Philip Quinlan, Sivanendra Selvanayagam, Sudarshan Onkar, Charul Agrawal:
26.4 A 160-to-960MHz ETSI class-1-compliant IoE transceiver with 100dB blocker rejection, 70dB ACR and 800pA standby current. 442-443 - Ken Yamamoto, Kenichi Nakano, Gaku Hidai, Yuya Kondo, Hitoshi Tomiyama, Hideyuki Takano, Fumitaka Kondo, Yusuke Shinohe, Hidenori Takeuchi, Nobuhisa Ozawa, Shingo Harada, Shinichiro Eto, Mari Kishikawa, Daisuke Ide, Hiroyasu Tagami, Masayuki Katakura, Norio Shoji:
26.5 A 0.7V 1.5-to-2.3mW GNSS receiver with 2.5-to-3.8dB NF in 28nm FD-SOI. 444-445 - Sameed Hameed, Neha Sinha, Mansour Rachid, Sudhakar Pamarti:
26.6 A programmable receiver front-end achieving >17dBm IIP3 at <1.25×BW frequency offset. 446-447 - Yao Shi, Myungjoon Choi, Ziyun Li, Gyouho Kim, Zhiyoong Foo, Hun-Seok Kim, David D. Wentzloff, David T. Blaauw:
26.7 A 10mm3 syringe-implantable near-field radio system on glass substrate. 448-449 - Nathan E. Roberts, Kyle Craig, Aatmesh Shrivastava, Stuart N. Wooters, Yousef Shakhsheer, Benton H. Calhoun, David D. Wentzloff:
26.8 A 236nW -56.5dBm-sensitivity bluetooth low-energy wakeup receiver with energy harvesting in 65nm CMOS. 450-451 - Gengzhen Qi, Pui-In Mak, Rui Paulo Martins:
26.9 A 0.038mm2 SAW-less multiband transceiver using an N-Path SC gain loop. 452-454 - Stéphane Le Tual, Kostas Doris:
Session 27 overview: Hybrid and nyquist data converters. 454-455 - Shiyu Su, Mike Shuo-Wei Chen:
27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS. 456-457 - Yun-Shiang Shu, Liang-Ting Kuo, Tien-Yu Lo:
27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS. 458-459 - Kyojin David Choo, John Bell, Michael P. Flynn:
27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC. 460-461 - Chun-Cheng Liu:
27.4 A 0.35mW 12b 100MS/s SAR-assisted digital slope ADC in 28nm CMOS. 462-463 - Matt Straayer, Jim Bales, Dwight Birdsall, Denis C. Daly, Phillip Elliott, Bill Foley, Roy Mason, Vikas Singh, Xuejin Wang:
27.5 A 4GS/s time-interleaved RF ADC in 65nm CMOS with 4GHz input bandwidth. 464-465 - Jiangfeng Wu, Acer Wei-Te Chou, Tianwei Li, Rong Wu, Tao Wang, Giuseppe Cusmai, Sha-Ting Lin, Cheng-Hsun Yang, Greg Unruh, Sunny Raj Dommaraju, Mo M. Zhang, Po Tang Yang, Wei-Ting Lin, Xi Chen, Dongsoo Koh, Qingqi Dou, Hemasundar Mohan Geddada, Juo-Jung Hung, Massimo Brandolini, Young Shin, Hung Sen Huang, Chun-Ying Chen, Ardie G. Venes:
27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS. 466-467 - Chin-Yu Lin, Yen-Hsin Wei, Tai-Cheng Lee:
27.7 A 10b 2.6GS/s time-interleaved SAR ADC with background timing-skew calibration. 468-469 - Alessandro Venca, Nicola Ghittori, Alessandro Bosi, Claudio Nani:
27.8 A 0.076mm2 12b 26.5mW 600MS/s 4×-interleaved subranging SAR-ΔΣ ADC with on-chip buffer in 28nm CMOS. 470-472 - Peter Wu, Jan Genoe:
Session 28 overview: Biological sensors for point of care. 472-473 - Ka-Meng Lei, Hadi Heidari, Pui-In Mak, Man-Kay Law, Franco Maloberti, Rui Paulo Martins:
28.1 A handheld 50pM-sensitivity micro-NMR CMOS platform with B-field stabilization for multi-type biological/chemical assays. 474-475 - Jonas Handwerker, Benedikt Schlecker, Ulrich Wachter, Peter Radermacher, Maurits Ortmanns, Jens Anders:
28.2 A 14GHz battery-operated point-of-care ESR spectrometer based on a 0.13µm CMOS ASIC. 476-477 - Takeshi Mitsunaka, Nobuyuki Ashida, Akira Saito, Kunihiko Iizuka, Tetsuhito Suzuki, Yuichi Ogawa, Minoru Fujishima:
28.3 CMOS biosensor IC focusing on dielectric relaxations of biological water with 120GHz and 60GHz oscillator arrays. 478-479 - Mario Konijnenburg, Stefano Stanzione, Long Yan, Dong-Woo Jee, Julia Pettine, Roland Van Wegberg, Hyejung Kim, Chris van Liempd, Ram Fish, James Schuessler, Harmke de Groot, Chris Van Hoof, Refet Firat Yazicioglu, Nick Van Helleputte:
28.4 A battery-powered efficient multi-sensor acquisition system with simultaneous ECG, BIO-Z, GSR, and PPG. 480-481 - Rachit Mohan, Samira Zaliasl, Georges G. E. Gielen, Chris Van Hoof, Nick Van Helleputte, Refet Firat Yazicioglu:
28.5 A 0.6V 0.015mm2 time-based biomedical readout for ambulatory applications in 40nm CMOS. 482-483 - Wenlong Jiang, Vahagn Hokhikyan, Hariprasad Chandrakumar, Vaibhav Karkare, Dejan Markovic:
28.6 A ±50mV linear-input-range VCO-based neural-recording front-end with digital nonlinearity correction. 484-485 - Pietro Ciccarella, Marco Carminati, Marco Sampietro, Giorgio Ferrari:
28.7 CMOS monolithic airborne-particulate-matter detector based on 32 capacitive sensors with a resolution of 65zF rms. 486-488 - Vivek De, Kerry Bernstein, Takefumi Yoshikawa, Yusuf Leblebici, Marian Verhelst, Mahesh Mehendale, Makoto Nagata:
F1: Designing secure systems: Manufacturing, circuits and architectures. 492-494 - Kostas Doris, Alyosha C. Molnar, Xicheng Jiang, Seung-Tak Ryu:
F2: Data-converter calibration and dynamic-matching techniques. 495-497 - Stefano Pellerano, Ahmad Mirzaei, Chih-Ming Hung, Jan Craninckx, Kenichi Okada, Vojkan Vidojkovic:
F3: Radio architectures and circuits towards 5G. 498-501 - Ichiro Fujimori, Martin Brox, Elad Alon, Pavan Kumar Hanumolu, Gerrit den Besten, Hideyuki Nosaka:
F4: Emerging short-reach and high-density interconnect solutions for internet of everything. 502-505 - Makoto Ikeda, David Stoppa, Michiel A. P. Pertijs, Yusuke Oike, Maurits Ortmanns, Vadim Ivanov, Fu-Lung Hsueh:
F5: Advanced IC design for ultra-low-noise sensing. 506-509 - Kush Gulati, Refet Firat Yazicioglu, Antoine Dupret, Roman Genov, Peter Chung-Yu Wu, Long Yan:
F6: Circuit, systems and data processing for next-generation wearable and implantable medical devices. 510-513 - Jan Van der Spiegel, SeongHwan Cho, Denis Daly:
ES1: Student research preview. 514-516 - Dejan Markovic, Antoine Dupret, Atsuki Inoue:
ES2: Computing architectures paving the path to power efficiency. 517 - Xicheng Jiang, Axel Thomsen, Piero Malcovati, M.-C. Frank Chang:
EE1: Class of 2025 - Where will be the best jobs? 518 - Harish Krishnaswamy, Jan Craninckx, Tae Wook Kim:
EE2: Do we need to downscale our radios below 20nm? 519 - Harry Lee, Matt Straayer, Chris Mangelsdorf:
EE3: Survey says! 520 - Woogeun Rhee, Eric A. M. Klumperink, Hossein Hashemi:
EE4: Eureka! The best moments of solid-state circuit design in the 2000s. 521 - Wim Dehaene:
SC1: Circuits for the internet of everything. 522-523
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