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Link to original content: https://dblp.org/rec/journals/vlsisp/NevesF97.ris
Provider: Schloss Dagstuhl - Leibniz Center for Informatics Database: dblp computer science bibliography Content:text/plain; charset="utf-8" TY - JOUR ID - DBLP:journals/vlsisp/NevesF97 AU - Neves, José Luis AU - Friedman, Eby G. TI - Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations. JO - J. VLSI Signal Process. VL - 16 IS - 2-3 SP - 149 EP - 161 PY - 1997// DO - 10.1023/A:1007986907060 UR - https://doi.org/10.1023/A:1007986907060 ER -