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Link to original content: https://dblp.org/rec/journals/tvlsi/ZeghidACS23.html?view=bibtex
dblp: BibTeX record journals/tvlsi/ZeghidACS23

BibTeX record journals/tvlsi/ZeghidACS23

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@article{DBLP:journals/tvlsi/ZeghidACS23,
  author       = {Medien Zeghid and
                  Hassan Yousif Ahmed and
                  Abdellah Chehri and
                  Anissa Sghaier},
  title        = {Speed/Area-Efficient {ECC} Processor Implementation Over GF(2\({}^{\mbox{m}}\))
                  on {FPGA} via Novel Algorithm-Architecture Co-Design},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {31},
  number       = {8},
  pages        = {1192--1203},
  year         = {2023},
  url          = {https://doi.org/10.1109/TVLSI.2023.3268999},
  doi          = {10.1109/TVLSI.2023.3268999},
  timestamp    = {Sat, 05 Aug 2023 00:02:42 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ZeghidACS23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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