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Link to original content: https://dblp.org/rec/journals/tvlsi/XueDYWYY12.ris
Provider: Schloss Dagstuhl - Leibniz Center for Informatics Database: dblp computer science bibliography Content:text/plain; charset="utf-8" TY - JOUR ID - DBLP:journals/tvlsi/XueDYWYY12 AU - Xue, Jiying AU - Deng, Yangdong AU - Ye, Zuochang AU - Wang, Hongrui AU - Yang, Liu AU - Yu, Zhiping TI - A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit Optimization. JO - IEEE Trans. Very Large Scale Integr. Syst. VL - 20 IS - 3 SP - 498 EP - 511 PY - 2012// DO - 10.1109/TVLSI.2010.2102374 UR - https://doi.org/10.1109/TVLSI.2010.2102374 ER -