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https://dblp.org/rec/journals/tvlsi/RiepeSSB96.nt
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"Michael A. Riepe et al.: Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation. (1996)" .
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_:ID_9b6d6cecc5df729dae15ecc0a9d5b8dc . _:ID_9b6d6cecc5df729dae15ecc0a9d5b8dc
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"journals/tvlsi/RiepeSSB96" .
_:ID_a31a8c563af63160dc314c534db6d185 . _:ID_a31a8c563af63160dc314c534db6d185
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"10.1109/92.486085" .
"Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation." .
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"4"^^
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_:Sig_4dfb184eabf1e45960a398228fe82a98_1 . _:Sig_4dfb184eabf1e45960a398228fe82a98_1
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"Michael A. Riepe" . _:Sig_4dfb184eabf1e45960a398228fe82a98_1
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"1"^^
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_:Sig_4dfb184eabf1e45960a398228fe82a98_2 . _:Sig_4dfb184eabf1e45960a398228fe82a98_2
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"Jo\u00E3o P. Marques Silva" . _:Sig_4dfb184eabf1e45960a398228fe82a98_2
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"2"^^
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_:Sig_4dfb184eabf1e45960a398228fe82a98_3 . _:Sig_4dfb184eabf1e45960a398228fe82a98_3
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"Karem A. Sakallah" . _:Sig_4dfb184eabf1e45960a398228fe82a98_3
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"3"^^
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_:Sig_4dfb184eabf1e45960a398228fe82a98_4 . _:Sig_4dfb184eabf1e45960a398228fe82a98_4
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"Richard B. Brown" . _:Sig_4dfb184eabf1e45960a398228fe82a98_4
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"4"^^
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"113-129" .
"IEEE Trans. Very Large Scale Integr. Syst." .
"IEEE Trans. Very Large Scale Integr. Syst." .
"4" .
"1" .
"1996"^^
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"provenance information for RDF data of dblp record 'journals/tvlsi/RiepeSSB96'" .
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"2020-03-11T18:18:50+0100" .