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Link to original content: https://dblp.org/rec/journals/tches/FallnichLZG24.rdf
Daniel Fallnich et al.: Efficient ASIC Architecture for Low Latency Classic McEliece Decoding. (2024) journals/tches/FallnichLZG24 10.46586/TCHES.V2024.I2.403-425 Efficient ASIC Architecture for Low Latency Classic McEliece Decoding. 4 Daniel Fallnich 1 Christian Lanius 2 Shutao Zhang 3 Tobias Gemmeke 4 403-425 IACR Trans. Cryptogr. Hardw. Embed. Syst. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024 2 2024 provenance information for RDF data of dblp record 'journals/tches/FallnichLZG24' 2024-06-08T13:14:59+0200