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Link to original content: https://dblp.org/rec/journals/tcasI/TangLWXYL00YNL23.html?view=bibtex
dblp: BibTeX record journals/tcasI/TangLWXYL00YNL23

BibTeX record journals/tcasI/TangLWXYL00YNL23

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@article{DBLP:journals/tcasI/TangLWXYL00YNL23,
  author       = {Wenjun Tang and
                  Mingyen Lee and
                  Juejian Wu and
                  Yixin Xu and
                  Yao Yu and
                  Yongpan Liu and
                  Kai Ni and
                  Yu Wang and
                  Huazhong Yang and
                  Vijaykrishnan Narayanan and
                  Xueqing Li},
  title        = {FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully
                  Dynamic Access With Reduced Bitline Charging Activity and Recycled
                  Bitline Charge},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {70},
  number       = {6},
  pages        = {2398--2411},
  year         = {2023},
  url          = {https://doi.org/10.1109/TCSI.2023.3251961},
  doi          = {10.1109/TCSI.2023.3251961},
  timestamp    = {Thu, 15 Jun 2023 21:57:12 +0200},
  biburl       = {https://dblp.org/rec/journals/tcasI/TangLWXYL00YNL23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}