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Link to original content: https://dblp.org/rec/journals/tcasI/GaoXLUR23.xml
Zhen Gao 0005 Jiajun Xiao Qiang Liu 0011 Anees Ullah Pedro Reviriego A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs. 2003-2015 2023 May 70 IEEE Trans. Circuits Syst. I Regul. Pap. 5 https://doi.org/10.1109/TCSI.2023.3239040 db/journals/tcasI/tcasI70.html#GaoXLUR23