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Link to original content: https://dblp.org/rec/journals/tcas/KhaleghiA18.html?view=bibtex
dblp: BibTeX record journals/tcas/KhaleghiA18

BibTeX record journals/tcas/KhaleghiA18

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@article{DBLP:journals/tcas/KhaleghiA18,
  author       = {Behnam Khaleghi and
                  Hossein Asadi},
  title        = {A Resistive RAM-Based {FPGA} Architecture Equipped With Efficient
                  Programming Circuitry},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {65-I},
  number       = {7},
  pages        = {2196--2209},
  year         = {2018},
  url          = {https://doi.org/10.1109/TCSI.2017.2778113},
  doi          = {10.1109/TCSI.2017.2778113},
  timestamp    = {Fri, 14 May 2021 08:28:19 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/KhaleghiA18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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