Isao ShirakawaNoboru OkudaTakashi HaradaSadahiro TaniHiroshi OzakiA Layout System for the Random Logic Portion of an MOS LSI Chip.572-581198130IEEE Trans. Computers8db/journals/tc/tc30.html#ShirakawaOHTO81https://doi.org/10.1109/TC.1981.1675842http://doi.ieeecomputersociety.org/10.1109/TC.1981.1675842