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Link to original content: https://dblp.org/rec/journals/tc/ShirakawaOHTO81.xml
Isao Shirakawa Noboru Okuda Takashi Harada Sadahiro Tani Hiroshi Ozaki A Layout System for the Random Logic Portion of an MOS LSI Chip. 572-581 1981 30 IEEE Trans. Computers 8 db/journals/tc/tc30.html#ShirakawaOHTO81 https://doi.org/10.1109/TC.1981.1675842 http://doi.ieeecomputersociety.org/10.1109/TC.1981.1675842