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Link to original content: https://dblp.org/rec/journals/jssc/VreedeGWNJLST99.nt
. . . . "Leo C. N. de Vreede et al.: Bipolar transistor epilayer design using the MAIDS mixed-level simulator. (1999)" . . _:ID_7591958dc9ec8040ac65f8905108277f . _:ID_7591958dc9ec8040ac65f8905108277f . _:ID_7591958dc9ec8040ac65f8905108277f . _:ID_7591958dc9ec8040ac65f8905108277f . _:ID_7591958dc9ec8040ac65f8905108277f "journals/jssc/VreedeGWNJLST99" . _:ID_f0e2394e94919c03d855d7eb885c22b6 . _:ID_f0e2394e94919c03d855d7eb885c22b6 . _:ID_f0e2394e94919c03d855d7eb885c22b6 . _:ID_f0e2394e94919c03d855d7eb885c22b6 . _:ID_f0e2394e94919c03d855d7eb885c22b6 "10.1109/4.782094" . "Bipolar transistor epilayer design using the MAIDS mixed-level simulator." . . . . . . . . . . . . . . . . . . "8"^^ . _:Sig_e01422819583b5fc16e885841c9f5d3b_1 . _:Sig_e01422819583b5fc16e885841c9f5d3b_1 . _:Sig_e01422819583b5fc16e885841c9f5d3b_1 . _:Sig_e01422819583b5fc16e885841c9f5d3b_1 "Leo C. N. de Vreede" . _:Sig_e01422819583b5fc16e885841c9f5d3b_1 . _:Sig_e01422819583b5fc16e885841c9f5d3b_1 "1"^^ . _:Sig_e01422819583b5fc16e885841c9f5d3b_1 . _:Sig_e01422819583b5fc16e885841c9f5d3b_2 . _:Sig_e01422819583b5fc16e885841c9f5d3b_2 . _:Sig_e01422819583b5fc16e885841c9f5d3b_2 . _:Sig_e01422819583b5fc16e885841c9f5d3b_2 "Henk C. de Graaff" . _:Sig_e01422819583b5fc16e885841c9f5d3b_2 . _:Sig_e01422819583b5fc16e885841c9f5d3b_2 "2"^^ . _:Sig_e01422819583b5fc16e885841c9f5d3b_2 . _:Sig_e01422819583b5fc16e885841c9f5d3b_3 . _:Sig_e01422819583b5fc16e885841c9f5d3b_3 . _:Sig_e01422819583b5fc16e885841c9f5d3b_3 . _:Sig_e01422819583b5fc16e885841c9f5d3b_3 "Joost A. Willemen" . _:Sig_e01422819583b5fc16e885841c9f5d3b_3 . _:Sig_e01422819583b5fc16e885841c9f5d3b_3 "3"^^ . _:Sig_e01422819583b5fc16e885841c9f5d3b_3 . _:Sig_e01422819583b5fc16e885841c9f5d3b_4 . _:Sig_e01422819583b5fc16e885841c9f5d3b_4 . _:Sig_e01422819583b5fc16e885841c9f5d3b_4 . _:Sig_e01422819583b5fc16e885841c9f5d3b_4 "Wibo D. van Noort" . _:Sig_e01422819583b5fc16e885841c9f5d3b_4 . _:Sig_e01422819583b5fc16e885841c9f5d3b_4 "4"^^ . _:Sig_e01422819583b5fc16e885841c9f5d3b_4 . _:Sig_e01422819583b5fc16e885841c9f5d3b_5 . _:Sig_e01422819583b5fc16e885841c9f5d3b_5 . _:Sig_e01422819583b5fc16e885841c9f5d3b_5 . _:Sig_e01422819583b5fc16e885841c9f5d3b_5 "Rik Jos" . _:Sig_e01422819583b5fc16e885841c9f5d3b_5 . _:Sig_e01422819583b5fc16e885841c9f5d3b_5 "5"^^ . _:Sig_e01422819583b5fc16e885841c9f5d3b_5 . _:Sig_e01422819583b5fc16e885841c9f5d3b_6 . _:Sig_e01422819583b5fc16e885841c9f5d3b_6 . _:Sig_e01422819583b5fc16e885841c9f5d3b_6 . _:Sig_e01422819583b5fc16e885841c9f5d3b_6 "Lawrence E. Larson" . _:Sig_e01422819583b5fc16e885841c9f5d3b_6 . _:Sig_e01422819583b5fc16e885841c9f5d3b_6 "6"^^ . _:Sig_e01422819583b5fc16e885841c9f5d3b_6 . _:Sig_e01422819583b5fc16e885841c9f5d3b_7 . _:Sig_e01422819583b5fc16e885841c9f5d3b_7 . _:Sig_e01422819583b5fc16e885841c9f5d3b_7 . _:Sig_e01422819583b5fc16e885841c9f5d3b_7 "Jan W. Slotboom" . _:Sig_e01422819583b5fc16e885841c9f5d3b_7 . _:Sig_e01422819583b5fc16e885841c9f5d3b_7 "7"^^ . _:Sig_e01422819583b5fc16e885841c9f5d3b_7 . _:Sig_e01422819583b5fc16e885841c9f5d3b_8 . _:Sig_e01422819583b5fc16e885841c9f5d3b_8 . _:Sig_e01422819583b5fc16e885841c9f5d3b_8 . _:Sig_e01422819583b5fc16e885841c9f5d3b_8 "Joseph L. Tauritz" . _:Sig_e01422819583b5fc16e885841c9f5d3b_8 . _:Sig_e01422819583b5fc16e885841c9f5d3b_8 "8"^^ . _:Sig_e01422819583b5fc16e885841c9f5d3b_8 . . . . . "1331-1338" . "IEEE J. Solid State Circuits" . "IEEE J. Solid State Circuits" . "34" . "9" . "1999"^^ . "provenance information for RDF data of dblp record 'journals/jssc/VreedeGWNJLST99'" . . . . "2022-07-05T16:10:43+0200" .