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Link to original content: https://dblp.org/rec/journals/jssc/RajME16.rdf
Mayank Raj et al.: A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS. (2016) journals/jssc/RajME16 10.1109/JSSC.2016.2553040 A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS. 3 Mayank Raj 1 Manuel Monge 2 Azita Emami 3 1734-1743 IEEE J. Solid State Circuits IEEE J. Solid State Circuits 51 8 2016 provenance information for RDF data of dblp record 'journals/jssc/RajME16' 2021-10-14T09:13:34+0200