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Link to original content: https://dblp.org/rec/journals/jssc/ParkSCCKPPCKJKC21.rdf
Hyunsu Park et al.: A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. (2021) journals/jssc/ParkSCCKPPCKJKC21 10.1109/JSSC.2020.3045168 A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. 13 Hyunsu Park 1 Jincheol Sim 2 Yoonjae Choi 3 Jonghyuck Choi 4 Youngwook Kwon 5 Seungwoo Park 6 Gyutae Park 7 Jinil Chung 8 Kyeong-Min Kim 9 Hae-Kang Jung 10 Hyungsoo Kim 11 Junhyun Chun 12 Chulwoo Kim 13 1886-1896 IEEE J. Solid State Circuits IEEE J. Solid State Circuits 56 6 2021 provenance information for RDF data of dblp record 'journals/jssc/ParkSCCKPPCKJKC21' 2021-06-15T17:21:48+0200