Jinwei Li et al.: A 7.6-12.3 GHz wide-band PLL with an ultra low reference spur -81.1 dBc in 0.13 μm CMOS technology. (2023)journals/ijcta/LiSHCJL2310.1002/CTA.3604A 7.6-12.3 GHz wide-band PLL with an ultra low reference spur -81.1 dBc in 0.13 μm CMOS technology.6Jinwei Li1Bing Sun2Jiawei Huang3Hudong Chang4Rui Jia5Honggang Liu63003-3016Int. J. Circuit Theory Appl.Int. J. Circuit Theory Appl.5172023--07provenance information for RDF data of dblp record 'journals/ijcta/LiSHCJL23'2023-08-05T00:02:41+0200