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Link to original content: https://dblp.org/rec/journals/iet-cds/ArnaldoRAH12.ris
Provider: Schloss Dagstuhl - Leibniz Center for Informatics Database: dblp computer science bibliography Content:text/plain; charset="utf-8" TY - JOUR ID - DBLP:journals/iet-cds/ArnaldoRAH12 AU - Arnaldo, Ignacio AU - Risco-Martín, José Luis AU - Ayala, José Luis AU - Hidalgo, José Ignacio TI - Power profiling-guided floorplanner for 3D multi-processor systems-on-chip. JO - IET Circuits Devices Syst. VL - 6 IS - 5 SP - 322 EP - 329 PY - 2012// DO - 10.1049/IET-CDS.2011.0350 UR - https://doi.org/10.1049/iet-cds.2011.0350 UR - https://www.wikidata.org/entity/Q57698169 ER -