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"Error Identification in At-Speed Scan BIST Environment in the Presence of ..."

Yoshiyuki Nakamura et al. (2006)

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DOI: 10.1093/IETISY/E89-D.3.1165

access: closed

type: Journal Article

metadata version: 2020-04-11

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Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara:
Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch. IEICE Trans. Inf. Syst. 89-D(3): 1165-1172 (2006)

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