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Link to original content: https://dblp.org/rec/journals/ieiceee/YangLC19.ris
Provider: Schloss Dagstuhl - Leibniz Center for Informatics Database: dblp computer science bibliography Content:text/plain; charset="utf-8" TY - JOUR ID - DBLP:journals/ieiceee/YangLC19 AU - Yang, Yuheng AU - Liu, Xueyong AU - Chen, Jie TI - An architecture design for anti-jamming circuit with low power and low area cost in high-precision GNSS receiver chip. JO - IEICE Electron. Express VL - 16 IS - 10 SP - 20190179 PY - 2019// DO - 10.1587/ELEX.16.20190179 UR - https://doi.org/10.1587/elex.16.20190179 ER -