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https://dblp.org/rec/journals/cal/Zhang06.nt
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"Chuanjun Zhang: Balanced instruction cache: reducing conflict misses of direct-mapped caches through balanced subarray accesses. (2006)" .
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_:ID_42cc3c5ab86e367f9c3c4b8232961180 . _:ID_42cc3c5ab86e367f9c3c4b8232961180
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"journals/cal/Zhang06" .
_:ID_5ecf6f2c4f1f33fcd805bfe5c001723f . _:ID_5ecf6f2c4f1f33fcd805bfe5c001723f
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"10.1109/L-CA.2006.3" .
"Balanced instruction cache: reducing conflict misses of direct-mapped caches through balanced subarray accesses." .
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"1"^^
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_:Sig_5f970cff5b3159c3b9071c26d55934c4_1 . _:Sig_5f970cff5b3159c3b9071c26d55934c4_1
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"Chuanjun Zhang" . _:Sig_5f970cff5b3159c3b9071c26d55934c4_1
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"1"^^
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"2-5" .
"IEEE Comput. Archit. Lett." .
"IEEE Comput. Archit. Lett." .
"5" .
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"2006"^^
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"provenance information for RDF data of dblp record 'journals/cal/Zhang06'" .
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"2020-03-15T19:44:18+0100" .
