BibTeX record conf/vlsit/ZhuZWWLWW22

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@inproceedings{DBLP:conf/vlsit/ZhuZWWLWW22,
  author       = {Wei Zhu and
                  Jian Zhang and
                  Jiawen Wang and
                  Ruitao Wang and
                  Chenguang Li and
                  Kai Wang and
                  Yan Wang},
  title        = {A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB,
                  14.8{\%} {TX} {PAE} in 65nm {CMOS} Process and +51dBm Array {EIRP}},
  booktitle    = {{IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
                  and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022},
  pages        = {128--129},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830350},
  doi          = {10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830350},
  timestamp    = {Mon, 06 Feb 2023 15:41:56 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsit/ZhuZWWLWW22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}