Provider: Schloss Dagstuhl - Leibniz Center for Informatics
Database: dblp computer science bibliography
Content:text/plain; charset="utf-8"
TY - CPAPER
ID - DBLP:conf/vlsic/PalPFGTRXZAWBCC19
AU - Pal, Subhankar
AU - Park, Dong-Hyeon
AU - Feng, Siying
AU - Gao, Paul
AU - Tan, Jielun
AU - Rovinski, Austin
AU - Xie, Shaolin
AU - Zhao, Chun
AU - Amarnath, Aporva
AU - Wesley, Timothy
AU - Beaumont, Jonathan
AU - Chen, Kuan-Yu
AU - Chakrabarti, Chaitali
AU - Taylor, Michael B.
AU - Mudge, Trevor N.
AU - Blaauw, David T.
AU - Kim, Hun-Seok
AU - Dreslinski, Ronald G.
TI - A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
BT - 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019
SP - 150
EP -
PY - 2019//
DO - 10.23919/VLSIC.2019.8778147
UR - https://doi.org/10.23919/VLSIC.2019.8778147
ER -
