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Link to original content: https://dblp.org/rec/conf/vlsic/LinHTTHCHHCGFRL19.rdf
Mu-Shan Lin et al.: A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing. (2019) conf/vlsic/LinHTTHCHHCGFRL19 10.23919/VLSIC.2019.8778161 A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing. 17 Mu-Shan Lin 1 Tze-Chiang Huang 2 Chien-Chun Tsai 3 King-Ho Tam 4 Kenny Cheng-Hsiang Hsieh 5 Tom Chen 0002 6 Wen-Hung Huang 7 Jack Hu 8 Yu-Chi Chen 9 Sandeep Kumar Goel 10 Chin-Ming Fu 11 Stefan Rusu 12 Chao-Chieh Li 13 Sheng-Yao Yang 14 Mei Wong 15 Shu-Chun Yang 16 Frank Lee 17 28- VLSI Circuits VLSI Circuits 2019 2019 provenance information for RDF data of dblp record 'conf/vlsic/LinHTTHCHHCGFRL19' 2020-04-02T09:00:12+0200