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Link to original content: https://dblp.org/rec/conf/vlsi/PoittevinMOMLDB20.xml
Arnaud Poittevin Chhandak Mukherjee Ian O'Connor Cristell Maneux Guilhem Larrieu Marina Deng Sébastien Le Beux François Marc Aurélie Lecestre Cédric Marchand 0002 Abhishek Kumar 3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. 301-321 2020 VLSI-SoC (Selected Papers) https://doi.org/10.1007/978-3-030-81641-4_14 conf/vlsi/2020socs db/conf/vlsi/vlsisoc2020s.html#PoittevinMOMLDB20