Provider: Schloss Dagstuhl - Leibniz Center for Informatics
Database: dblp computer science bibliography
Content:text/plain; charset="utf-8"
TY - CPAPER
ID - DBLP:conf/patmos/InnocentiWBJPSL15
AU - Innocenti, Jordan
AU - Welter, Loïc
AU - Borrel, Nicolas
AU - Julien, Franck
AU - Portal, Jean-Michel
AU - Sonzogni, Jacques
AU - Lopez, Laurent
AU - Masson, Pascal
AU - Niel, Stephan
AU - Dreux, Philippe
AU - Castellan, Julia
TI - Dynamic current reduction of CMOS digital circuits through design and process optimization.
BT - 25th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2015, Salvador, Brazil, September 1-4, 2015
SP - 77
EP - 81
PY - 2015//
DO - 10.1109/PATMOS.2015.7347590
UR - https://doi.org/10.1109/PATMOS.2015.7347590
ER -
