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Link to original content: https://dblp.org/rec/conf/patmos/ArnaldoRAH11.ris
Provider: Schloss Dagstuhl - Leibniz Center for Informatics Database: dblp computer science bibliography Content:text/plain; charset="utf-8" TY - CPAPER ID - DBLP:conf/patmos/ArnaldoRAH11 AU - Arnaldo, Ignacio AU - Risco-Martín, José L. AU - Ayala, José L. AU - Hidalgo, José Ignacio TI - Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures. BT - Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings SP - 11 EP - 21 PY - 2011// DO - 10.1007/978-3-642-24154-3_2 UR - https://doi.org/10.1007/978-3-642-24154-3_2 UR - https://www.wikidata.org/entity/Q57698228 ER -