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https://dblp.org/rec/conf/mlcad/BustanyGGKKLP23.nt
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"Ismail Bustany et al.: The 2023 MLCAD FPGA Macro Placement Benchmark Design Suite and Contest Results. (2023)" .
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_:ID_9fe77720c53b63abb732d03c2515ad2c . _:ID_9fe77720c53b63abb732d03c2515ad2c
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"conf/mlcad/BustanyGGKKLP23" .
_:ID_a2eba72b549755a84bbee4392b3509fe . _:ID_a2eba72b549755a84bbee4392b3509fe
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"10.1109/MLCAD58807.2023.10299868" .
"The 2023 MLCAD FPGA Macro Placement Benchmark Design Suite and Contest Results." .
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"7"^^
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_:Sig_3c268a4ad58160ef5371e366355baa70_1 . _:Sig_3c268a4ad58160ef5371e366355baa70_1
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"Ismail Bustany" . _:Sig_3c268a4ad58160ef5371e366355baa70_1
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"1"^^
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_:Sig_3c268a4ad58160ef5371e366355baa70_2 . _:Sig_3c268a4ad58160ef5371e366355baa70_2
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"Grigor Gasparyan" . _:Sig_3c268a4ad58160ef5371e366355baa70_2
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"2"^^
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_:Sig_3c268a4ad58160ef5371e366355baa70_3 . _:Sig_3c268a4ad58160ef5371e366355baa70_3
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"Amit Gupta" . _:Sig_3c268a4ad58160ef5371e366355baa70_3
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"3"^^
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_:Sig_3c268a4ad58160ef5371e366355baa70_4 . _:Sig_3c268a4ad58160ef5371e366355baa70_4
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"Andrew B. Kahng" . _:Sig_3c268a4ad58160ef5371e366355baa70_4
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"4"^^
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_:Sig_3c268a4ad58160ef5371e366355baa70_5 . _:Sig_3c268a4ad58160ef5371e366355baa70_5
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"Meghraj Kalase" . _:Sig_3c268a4ad58160ef5371e366355baa70_5
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"5"^^
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_:Sig_3c268a4ad58160ef5371e366355baa70_6 . _:Sig_3c268a4ad58160ef5371e366355baa70_6
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"Wuxi Li" . _:Sig_3c268a4ad58160ef5371e366355baa70_6
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"6"^^
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_:Sig_3c268a4ad58160ef5371e366355baa70_7 . _:Sig_3c268a4ad58160ef5371e366355baa70_7
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"Bodhisatta Pramanik" . _:Sig_3c268a4ad58160ef5371e366355baa70_7
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"7"^^
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"1-6" .
"MLCAD" .
"MLCAD" .
"2023"^^
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"2023"^^
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"provenance information for RDF data of dblp record 'conf/mlcad/BustanyGGKKLP23'" .
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"2024-08-04T19:43:05+0200" .