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https://dblp.org/rec/conf/isvlsi/MaoYXYS22.nt
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"Gang Mao et al.: Automated Mapping of Asynchronous Circuits on FPGA under Timing Constraints. (2022)" .
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_:ID_c703d9c121230125d8bf0ea00bf2e664 . _:ID_c703d9c121230125d8bf0ea00bf2e664
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"conf/isvlsi/MaoYXYS22" .
_:ID_de9ef206342e62e8086c6ea1461af026 . _:ID_de9ef206342e62e8086c6ea1461af026
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"10.1109/ISVLSI54635.2022.00031" .
"Automated Mapping of Asynchronous Circuits on FPGA under Timing Constraints." .
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"5"^^
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_:Sig_ad91d508526caee1bf4d09e73d3c9420_1 . _:Sig_ad91d508526caee1bf4d09e73d3c9420_1
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"Gang Mao" . _:Sig_ad91d508526caee1bf4d09e73d3c9420_1
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"1"^^
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_:Sig_ad91d508526caee1bf4d09e73d3c9420_2 . _:Sig_ad91d508526caee1bf4d09e73d3c9420_2
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"Alex Yakovlev" . _:Sig_ad91d508526caee1bf4d09e73d3c9420_2
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"2"^^
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_:Sig_ad91d508526caee1bf4d09e73d3c9420_3 . _:Sig_ad91d508526caee1bf4d09e73d3c9420_3
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"Fei Xia 0001" . _:Sig_ad91d508526caee1bf4d09e73d3c9420_3
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"3"^^
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_:Sig_ad91d508526caee1bf4d09e73d3c9420_4 . _:Sig_ad91d508526caee1bf4d09e73d3c9420_4
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"Shengqi Yu" . _:Sig_ad91d508526caee1bf4d09e73d3c9420_4
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"4"^^
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_:Sig_ad91d508526caee1bf4d09e73d3c9420_5 . _:Sig_ad91d508526caee1bf4d09e73d3c9420_5
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"Rishad A. Shafik" . _:Sig_ad91d508526caee1bf4d09e73d3c9420_5
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"5"^^
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"104-109" .
"ISVLSI" .
"ISVLSI" .
"2022"^^
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"2022"^^
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"provenance information for RDF data of dblp record 'conf/isvlsi/MaoYXYS22'" .
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"2024-11-12T16:50:49+0100" .