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Link to original content: https://dblp.org/rec/conf/isvlsi/LiPLB22.xml
Xi Li Min Pan Tong Liu Peter A. Beerel Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic. 62-67 2022 ISVLSI https://doi.org/10.1109/ISVLSI54635.2022.00024 conf/isvlsi/2022 db/conf/isvlsi/isvlsi2022.html#LiPLB22