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Link to original content: https://dblp.org/rec/conf/isvlsi/CarpegnaSC22.ris
Provider: Schloss Dagstuhl - Leibniz Center for Informatics Database: dblp computer science bibliography Content:text/plain; charset="utf-8" TY - CPAPER ID - DBLP:conf/isvlsi/CarpegnaSC22 AU - Carpegna, Alessio AU - Savino, Alessandro AU - Carlo, Stefano Di TI - Spiker: an FPGA-optimized Hardware accelerator for Spiking Neural Networks. BT - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2022, Nicosia, Cyprus, July 4-6, 2022 SP - 14 EP - 19 PY - 2022// DO - 10.1109/ISVLSI54635.2022.00016 UR - https://doi.org/10.1109/ISVLSI54635.2022.00016 ER -