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Link to original content: https://dblp.org/rec/conf/isvlsi/CarpegnaSC22.nt
. . . . "Alessio Carpegna et al.: Spiker: an FPGA-optimized Hardware accelerator for Spiking Neural Networks. (2022)" . . _:ID_8cf6d9c7df8e5070de33ee684be78a71 . _:ID_8cf6d9c7df8e5070de33ee684be78a71 . _:ID_8cf6d9c7df8e5070de33ee684be78a71 . _:ID_8cf6d9c7df8e5070de33ee684be78a71 . _:ID_8cf6d9c7df8e5070de33ee684be78a71 "conf/isvlsi/CarpegnaSC22" . _:ID_bc2445478a8cb0ed31d8ccfd851207b6 . _:ID_bc2445478a8cb0ed31d8ccfd851207b6 . _:ID_bc2445478a8cb0ed31d8ccfd851207b6 . _:ID_bc2445478a8cb0ed31d8ccfd851207b6 . _:ID_bc2445478a8cb0ed31d8ccfd851207b6 "10.1109/ISVLSI54635.2022.00016" . "Spiker: an FPGA-optimized Hardware accelerator for Spiking Neural Networks." . . . . . . . . "3"^^ . _:Sig_504f79863b17afb4a18c8e26a770e9b5_1 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_1 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_1 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_1 "Alessio Carpegna" . _:Sig_504f79863b17afb4a18c8e26a770e9b5_1 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_1 "1"^^ . _:Sig_504f79863b17afb4a18c8e26a770e9b5_1 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_2 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_2 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_2 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_2 "Alessandro Savino" . _:Sig_504f79863b17afb4a18c8e26a770e9b5_2 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_2 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_2 "2"^^ . _:Sig_504f79863b17afb4a18c8e26a770e9b5_2 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_3 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_3 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_3 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_3 "Stefano Di Carlo" . _:Sig_504f79863b17afb4a18c8e26a770e9b5_3 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_3 . _:Sig_504f79863b17afb4a18c8e26a770e9b5_3 "3"^^ . _:Sig_504f79863b17afb4a18c8e26a770e9b5_3 . . . . . "14-19" . "ISVLSI" . "ISVLSI" . "2022"^^ . "2022"^^ . . "provenance information for RDF data of dblp record 'conf/isvlsi/CarpegnaSC22'" . . . . "2023-03-21T20:58:51+0100" .