Provider: Schloss Dagstuhl - Leibniz Center for Informatics
Database: dblp computer science bibliography
Content:text/plain; charset="utf-8"
TY - CPAPER
ID - DBLP:conf/iscas/MullerWSKS04
AU - Müller, Matthias
AU - Wortmann, Andreas
AU - Simon, Sven
AU - Kugel, Michael
AU - Schoenauer, Tim
TI - The impact of clock gating schemes on the power dissipation of synthesizable register files.
BT - Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004
SP - 609
EP - 612
PY - 2004//
ER -
