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Link to original content: https://dblp.org/rec/conf/iscas/MullerWSKS04.rdf
Matthias Müller et al.: The impact of clock gating schemes on the power dissipation of synthesizable register files. (2004) conf/iscas/MullerWSKS04 The impact of clock gating schemes on the power dissipation of synthesizable register files. 5 Matthias Müller 0002 1 Andreas Wortmann 0002 2 Sven Simon 0001 3 Michael Kugel 4 Tim Schoenauer 5 609-612 ISCAS (2) ISCAS (2) 2004 2004 provenance information for RDF data of dblp record 'conf/iscas/MullerWSKS04' 2020-11-27T19:26:08+0100