Shuguang Zhao et al.: Design and Implementation of an Improved GEP Algorithm for Synthesis of Reversible Logic Circuits. (2017)conf/iccae/ZhaoWX1710.1145/3057039.3057060Design and Implementation of an Improved GEP Algorithm for Synthesis of Reversible Logic Circuits.3Shuguang Zhao1Chaozheng Wang2Kaixiang Xia3174-178ICCAEICCAE20172017provenance information for RDF data of dblp record 'conf/iccae/ZhaoWX17'2021-11-17T15:27:52+0100