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Link to original content: https://dblp.org/rec/conf/iccae/ZhaoWX17.rdf
Shuguang Zhao et al.: Design and Implementation of an Improved GEP Algorithm for Synthesis of Reversible Logic Circuits. (2017) conf/iccae/ZhaoWX17 10.1145/3057039.3057060 Design and Implementation of an Improved GEP Algorithm for Synthesis of Reversible Logic Circuits. 3 Shuguang Zhao 1 Chaozheng Wang 2 Kaixiang Xia 3 174-178 ICCAE ICCAE 2017 2017 provenance information for RDF data of dblp record 'conf/iccae/ZhaoWX17' 2021-11-17T15:27:52+0100