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Link to original content: https://dblp.org/rec/conf/glvlsi/ItohYK07.xml
Kiyoo Itoh 0001 Masanao Yamaoka Takayuki Kawahara Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. 529-533 2007 conf/glvlsi/2007 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1228784.1228789 db/conf/glvlsi/glvlsi2007.html#ItohYK07