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https://dblp.org/rec/conf/glvlsi/CuestaAHPAM10.nt
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"David Cuesta et al.: Thermal-aware floorplanning exploration for 3D multi-core architectures. (2010)" .
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_:ID_fdb48c27e4300f73105d0bfbc82655b2 . _:ID_fdb48c27e4300f73105d0bfbc82655b2
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"conf/glvlsi/CuestaAHPAM10" .
_:ID_0561ab915946ce36af11c3e052b6eba0 . _:ID_0561ab915946ce36af11c3e052b6eba0
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"10.1145/1785481.1785505" .
_:ID_ec7f66544f7bf87a456888650a49d03f . _:ID_ec7f66544f7bf87a456888650a49d03f
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"Q57698315" .
"Thermal-aware floorplanning exploration for 3D multi-core architectures." .
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"6"^^
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_:Sig_b0423789ca42812fc2eab75dae38c76e_1 . _:Sig_b0423789ca42812fc2eab75dae38c76e_1
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"David Cuesta" . _:Sig_b0423789ca42812fc2eab75dae38c76e_1
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"1"^^
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_:Sig_b0423789ca42812fc2eab75dae38c76e_2 . _:Sig_b0423789ca42812fc2eab75dae38c76e_2
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"Jos\u00E9 Luis Ayala" . _:Sig_b0423789ca42812fc2eab75dae38c76e_2
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"2"^^
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_:Sig_b0423789ca42812fc2eab75dae38c76e_3 . _:Sig_b0423789ca42812fc2eab75dae38c76e_3
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"Jos\u00E9 Ignacio Hidalgo" . _:Sig_b0423789ca42812fc2eab75dae38c76e_3
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"3"^^
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_:Sig_b0423789ca42812fc2eab75dae38c76e_4 . _:Sig_b0423789ca42812fc2eab75dae38c76e_4
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"Massimo Poncino" . _:Sig_b0423789ca42812fc2eab75dae38c76e_4
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"4"^^
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_:Sig_b0423789ca42812fc2eab75dae38c76e_5 . _:Sig_b0423789ca42812fc2eab75dae38c76e_5
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"Andrea Acquaviva" . _:Sig_b0423789ca42812fc2eab75dae38c76e_5
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"5"^^
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_:Sig_b0423789ca42812fc2eab75dae38c76e_6 . _:Sig_b0423789ca42812fc2eab75dae38c76e_6
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"Enrico Macii" . _:Sig_b0423789ca42812fc2eab75dae38c76e_6
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"6"^^
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"99-102" .
"ACM Great Lakes Symposium on VLSI" .
"ACM Great Lakes Symposium on VLSI" .
"2010"^^
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"2010"^^
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"provenance information for RDF data of dblp record 'conf/glvlsi/CuestaAHPAM10'" .
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"2018-11-14T10:55:27+0100" .
