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Link to original content: https://dblp.org/rec/conf/fpl/BeuxMD07.rdf
Sébastien Le Beux et al.: A Design Flow to Map Parallel Applications onto FPGAs. (2007) conf/fpl/BeuxMD07 10.1109/FPL.2007.4380727 A Design Flow to Map Parallel Applications onto FPGAs. 3 Sébastien Le Beux 1 Philippe Marquet 2 Jean-Luc Dekeyser 3 605-608 FPL FPL 2007 2007 provenance information for RDF data of dblp record 'conf/fpl/BeuxMD07' 2017-05-21T00:20:37+0200