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Link to original content: https://dblp.org/rec/conf/date/FeketeKT01.xml
Sándor P. Fekete Ekkehard Köhler Jürgen Teich Optimal FPGA module placement with temporal precedence constraints. 658-667 2001 conf/date/2001 DATE https://doi.org/10.1109/DATE.2001.915093 https://doi.ieeecomputersociety.org/10.1109/DATE.2001.915093 http://dl.acm.org/citation.cfm?id=367842 db/conf/date/date2001.html#FeketeKT01