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ORCIDBrad L. Hutchings
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- affiliation: Brigham Young University, Provo, Utah, USA
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2020 – today
- 2023
[c63]Hayden Cook, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders:
Improving the Reliability of FPGA CRO PUFs. FPL 2023: 311-316- 2022
- [j14]Eli Cahill
, Brad L. Hutchings, Jeffrey Goeders:
Approaches for FPGA Design Assurance. ACM Trans. Reconfigurable Technol. Syst. 15(3): 28:1-28:29 (2022) - [j13]Hayden Cook, Jacob Arscott, Brent George, Tanner Gaskin, Jeffrey Goeders, Brad L. Hutchings:
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits. ACM Trans. Reconfigurable Technol. Syst. 15(4): 41:1-41:33 (2022) - [c62]Hayden Cook, Jonathan Thompson, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders:
Cloning the Unclonable: Physically Cloning an FPGA Ring-Oscillator PUF. FPT 2022: 1-10 - 2020
- [c61]Tanner Gaskin, Hayden Cook, Wesley Stirk, Robert Lucas, Jeffrey Goeders, Brad L. Hutchings:
Using Novel Configuration Techniques for Accelerated FPGA Aging. FPL 2020: 169-175
2010 – 2019
- 2019
- [c60]Robert Hale, Brad L. Hutchings:
Preallocating Resources for Distributed Memory Based FPGA Debug. FPL 2019: 384-390 - 2018
- [j12]Joshua S. Monson, Brad L. Hutchings:
Enhancing debug observability for HLS-based FPGA circuits through source-to-source compilation. J. Parallel Distributed Comput. 117: 148-160 (2018) - [c59]Jeffrey Goeders, Tanner Gaskin, Brad L. Hutchings:
Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ. FCCM 2018: 149-156 - [c58]Robert Hale, Brad L. Hutchings:
Enabling Low Impact, Rapid Debug for Highly Utilized FPGA Designs. FPL 2018: 81-84 - [c57]Robert Hale, Brad L. Hutchings:
Distributed-Memory Based FPGA Debug: Design Timing Impact. FPT 2018: 350-353 - [c56]Adam Hastings, Sean Jensen, Jeffrey Goeders, Brad L. Hutchings:
Using Physical and Functional Comparisons to Assure 3rd-Party IP for Modern FPGAs. IVSW 2018: 80-86 - 2017
- [c55]Brad L. Hutchings, Michael J. Wirthlin:
Rapid implementation of a partially reconfigurable video system with PYNQ. FPL 2017: 1-8 - 2016
- [c54]Travis Haroldsen, Brent E. Nelson, Brad L. Hutchings:
Packing a modern Xilinx FPGA using RapidSmith. ReConFig 2016: 1-6 - 2015
- [c53]Joshua S. Monson, Brad L. Hutchings:
Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs. FPGA 2015: 5-8 - [c52]Travis Haroldsen, Brent E. Nelson, Brad L. Hutchings:
RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs. FPGA 2015: 66-69 - [c51]Joshua S. Monson, Brad L. Hutchings:
Using source-to-source compilation to instrument circuits for debug with High Level Synthesis. FPT 2015: 48-55 - [c50]Joshua S. Monson, Brad L. Hutchings:
Using shadow pointers to trace C pointer values in FPGA circuits. ReConFig 2015: 1-6 - 2014
- [c49]Brad L. Hutchings, Jared Keeley:
Rapid Post-Map Insertion of Embedded Logic Analyzers for Xilinx FPGAs. FCCM 2014: 72-79 - [c48]Brad L. Hutchings, Joshua S. Monson, Danny Savory, Jared Keeley:
A power side-channel-based digital to analog converterfor Xilinx FPGAs. FPGA 2014: 113-116 - [c47]Joshua S. Monson, Brad L. Hutchings:
New approaches for in-system debug of behaviorally-synthesized FPGA circuits. FPL 2014: 1-6 - 2013
- [c46]Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings:
Implementing high-performance, low-power FPGA-based optical flow accelerators in C. ASAP 2013: 363-369 - [c45]Christopher Lavin, Brent E. Nelson, Brad L. Hutchings:
Impact of hard macro size on FPGA clock rate and place/route time. FPL 2013: 1-6 - [c44]Christopher Lavin, Brent E. Nelson, Brad L. Hutchings:
Improving clock-rate of hard-macro designs. FPT 2013: 246-253 - [c43]Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings:
Optimization techniques for a high level synthesis implementation of the Sobel filter. ReConFig 2013: 1-6 - [e2]Brad L. Hutchings, Vaughn Betz:
The 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '13, Monterey, CA, USA, February 11-13, 2013. ACM 2013, ISBN 978-1-4503-1887-7 [contents] - 2012
- [j11]Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings:
A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform. Int. J. Reconfigurable Comput. 2012: 850487:1-850487:11 (2012) - [c42]Jaren Lamprecht, Brad L. Hutchings:
Profiling FPGA floor-planning effects on timing closure. FPL 2012: 151-156 - [e1]Katherine Compton, Brad L. Hutchings:
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, FPGA 2012, Monterey, California, USA, February 22-24, 2012. ACM 2012, ISBN 978-1-4503-1155-7 [contents] - [i2]Peter M. Athanas, Brad L. Hutchings, Kentaro Sano:
The NII Shonan Configurable Computing Workshop (NII Shonan Meeting 2012-11). NII Shonan Meet. Rep. 2012 (2012) - 2011
- [c41]Peter Lieber, Brad L. Hutchings:
FPGA Communication Framework. FCCM 2011: 69-72 - [c40]Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings:
HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping. FCCM 2011: 117-124 - [c39]Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings:
RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs. FPL 2011: 349-355 - 2010
- [c38]Christopher Lavin, Marc Padilla, Subhrashankha Ghosh, Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin:
Using Hard Macros to Reduce FPGA Compilation Time. FPL 2010: 438-441 - [c37]Christopher Lavin, Marc Padilla, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings:
Rapid prototyping tools for FPGA designs: RapidSmith. FPT 2010: 353-356 - [c36]Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings:
Fault Injection Results of Linux Operating on an FPGA Embedded Platform. ReConFig 2010: 37-42
2000 – 2009
- 2009
- [c35]Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis:
Optical Flow on the Ambric Massively Parallel Processor Array (MPPA). FCCM 2009: 141-148 - [c34]Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis:
Comparing fine-grained performance on the Ambric MPPA against an FPGA. FPL 2009: 174-179 - 2008
- [j10]Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin:
Design, Debug, Deploy: The Creation of Configurable Computing Applications. J. Signal Process. Syst. 53(1-2): 187-196 (2008) - [c33]Brent E. Nelson, Michael J. Wirthlin, Brad L. Hutchings, Peter M. Athanas, Shawn A. Bohner:
Design Productivity for Configurable Computing. ERSA 2008: 57-66 - 2004
- [j9]Brad L. Hutchings, Brent E. Nelson:
GigaOp DSP on FPGA. J. VLSI Signal Process. 36(1): 41-55 (2004) - [c32]André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica:
What is the right model for programming and using modern FPGAs? FPGA 2004: 119 - 2003
- [c31]Robert Reuss, Jose L. Muñoz, Toshiaki Miyazaki, Nader Bagherzadeh, Prith Banerjee, Brad L. Hutchings, Brian Schott:
Adaptive computing: what can it do, where can it go? ASP-DAC 2003: 463 - [c30]K. Scott Hemmert, Brad L. Hutchings:
Issues in debugging highly parallel FPGA-based applications derived from source code. ASP-DAC 2003: 483-488 - [c29]Preston A. Jackson, Brad L. Hutchings, Justin L. Tripp:
Simulation and Synthesis of CSP-based Interprocess Communication. FCCM 2003: 218-227 - [c28]K. Scott Hemmert, Justin L. Tripp, Brad L. Hutchings, Preston A. Jackson:
Source Level Debugger for the Sea Cucumber Synthesizing Compiler. FCCM 2003: 228- - [c27]Anthony L. Slade, Brent E. Nelson, Brad L. Hutchings:
Reconfigurable Computing Application Frameworks. FCCM 2003: 251- - 2002
- [j8]David Eppstein, Marshall W. Bern, Brad L. Hutchings:
Algorithms for Coloring Quadtrees. Algorithmica 32(1): 87-94 (2002) - [c26]Brad L. Hutchings, R. Franklin, D. Carver:
Assisting Network Intrusion Detection with Reconfigurable Hardware. FCCM 2002: 111-120 - [c25]Wesley J. Landaker, Michael J. Wirthlin, Brad L. Hutchings:
Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System. FPL 2002: 806-815 - [c24]Justin L. Tripp, Preston A. Jackson, Brad L. Hutchings:
Sea Cucumber: A Synthesizing Compiler for FPGAs. FPL 2002: 875-885 - 2001
- [j7]Brad L. Hutchings, Brent E. Nelson:
Unifying simulation and execution in a design environment for FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 201-205 (2001) - [j6]Peter Bellows, Brad L. Hutchings:
Designing Run-Time Reconfigurable Systems with JHDL. J. VLSI Signal Process. 28(1-2): 29-45 (2001) - [c23]Paul S. Graham, Brent E. Nelson, Brad L. Hutchings:
Instrumenting Bitstreams for Debugging FPGA Circuits. FCCM 2001: 41-50 - [c22]K. Scott Hemmert, Brad L. Hutchings, Anshul Malvi:
An Application-Specific Compiler for High-Speed Binary Image Morphology. FCCM 2001: 199-208 - [c21]Michael J. Wirthlin, Brad L. Hutchings, Carl D. Worth:
Synthesizing RTL Hardware from Java Byte Codes. FPL 2001: 123-132 - [c20]Timothy Wheeler, Paul S. Graham, Brent E. Nelson, Brad L. Hutchings:
Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification. FPL 2001: 483-492 - [c19]Brad L. Hutchings, Brent E. Nelson:
Gigaop DSP on FPGA. ICASSP 2001: 885-888 - 2000
- [j5]Brad L. Hutchings, Brent E. Nelson, Michael J. Wirthlin:
Designing and Debugging Custom Computing Applications. IEEE Des. Test Comput. 17(1): 20-28 (2000) - [c18]Brad L. Hutchings, Brent E. Nelson:
Using general-purpose programming languages for FPGA design. DAC 2000: 561-566 - [c17]Paul S. Graham, Brad L. Hutchings, Brent E. Nelson:
Improving the FPGA Design Process through Determining and Applying Logical-to-Physical Design Mappings. FCCM 2000: 305-306
1990 – 1999
- 1999
- [c16]Brad L. Hutchings, Peter Bellows, Joseph Hawkins, K. Scott Hemmert, Brent E. Nelson, Mike Rytting:
A CAD Suite for High-Performance FPGA Design. FCCM 1999: 12-24 - [c15]Alan Marshall, Tony Stansfield, Igor Kostarnov, Jean Vuillemin, Brad L. Hutchings:
A Reconfigurable Arithmetic Array for Multimedia Application. FPGA 1999: 135-143 - [i1]David Eppstein, Marshall W. Bern, Brad L. Hutchings:
Algorithms for Coloring Quadtrees. CoRR cs.CG/9907030 (1999) - 1998
- [j4]John D. Villasenor, Brad L. Hutchings:
The flexibility of configurable computing. IEEE Signal Process. Mag. 15(5): 67-84 (1998) - [j3]Michael J. Wirthlin, Brad L. Hutchings:
Improving functional density using run-time circuit reconfiguration [FPGAs]. IEEE Trans. Very Large Scale Integr. Syst. 6(2): 247-256 (1998) - [c14]Peter Bellows, Brad L. Hutchings:
JHDL - An HDL for Reconfigurable Systems. FCCM 1998: 175-184 - 1997
- [c13]Michael Rencher, Brad L. Hutchings:
Automated target recognition on SPLASH 2. FCCM 1997: 192-200 - [c12]Michael J. Wirthlin, Brad L. Hutchings:
Improving Functional Density Through Run-Time Constant Propagation. FPGA 1997: 86-92 - [c11]Brad L. Hutchings:
Exploiting reconfigurability through domain-specific systems. FPL 1997: 193-202 - [c10]Brad L. Hutchings:
ASICs, Processors, and Configurable Computing. HICSS (1) 1997: 719 - 1996
- [j2]James G. Eldredge, Brad L. Hutchings:
Run-Time Reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs. J. VLSI Signal Process. 12(1): 67-86 (1996) - [c9]Pieter J. Bakkes, Jan J. Du Plessis, Brad L. Hutchings:
Mixing fixed and reconfigurable logic for array processing. FCCM 1996: 118-125 - [c8]David A. Clark, Brad L. Hutchings:
Supporting FPGA microprocessors through retargetable software tools. FCCM 1996: 195-203 - [c7]Michael J. Wirthlin, Brad L. Hutchings:
Sequencing Run-Time Reconfigured Hardware with Software. FPGA 1996: 122-128 - 1995
- [c6]James D. Hadley, Brad L. Hutchings:
Design methodologies for partially reconfigured systems. FCCM 1995: 78-84 - [c5]Michael J. Wirthlin, Brad L. Hutchings:
A dynamic instruction set computer. FCCM 1995: 99-109 - [c4]Russell J. Petersen, Brad L. Hutchings:
An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing. FPL 1995: 293-302 - [c3]Brad L. Hutchings, Michael J. Wirthlin:
Implementation Approaches for Reconfigurable Logic Applications. FPL 1995: 419-428 - 1994
- [c2]Brad L. Hutchings, Tony M. Carter:
High-Speed Circuit Design: CAD Tools and Computational Challenges. HICSS (1) 1994: 26-35 - [c1]Brad L. Hutchings, A. R. Grahn, Russell J. Petersen:
Multiple-Layer Cross-Field Ultrasonic Tactile Sensor. ICRA 1994: 2522-2528
1980 – 1989
- 1989
- [j1]Bir Bhanu, Brad L. Hutchings, Kent F. Smith:
VLSI design and implementation of a real-time image segmentation processor. Mach. Vis. Appl. 3(1): 21-44 (1989)
Coauthor Index
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