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ORCIDMladen Berekovic
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- affiliation: Braunschweig University of Technology, Germany
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2020 – today
- 2024
[j27]Enkele Rama
, Mouadh Ayache, Rainer Buchty, Bernhard Bauer, Matthias Korb, Mladen Berekovic, Saleh Mulhem:
Trustworthy Integrated Circuits: From Safety to Security and Beyond. IEEE Access 12: 69603-69632 (2024)- [j26]Saleh Mulhem, Felix Muuss, Christian Ewert, Rainer Buchty, Mladen Berekovic:
ML-Based Trojan Classification: Repercussions of Toxic Boundary Nets. IEEE Embed. Syst. Lett. 16(3): 251-254 (2024) - [c82]Wadid Foudhaili, Anouar Nechi, Celine Thermann, Mohammad Al Johmani, Rainer Buchty, Mladen Berekovic, Saleh Mulhem:
Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach. ARC 2024: 48-62 - [c81]Patrick Schmidt, Iuliia Topko, Matthias Stammler, Tanja Harbaum, Jürgen Becker, Rico Berner, Omar Ahmed, Jakub Jagielski, Thomas Seidler, Markus Abel, Marius Kreutzer, Maximilian Kirschner, Victor Pazmino Betancourt, Robin Sehm, Lukas Groth, Andrija Neskovic, Rolf Meyer, Saleh Mulhem, Mladen Berekovic, Matthias Probst, Manuel Brosch, Georg Sigl, Thomas Wild, Matthias Ernst, Andreas Herkersdorf, Florian Aigner, Stefan Hommes, Sebastian Lauer, Maximilian Seidler, Thomas Raste, Gasper Skvarc Bozic, Ibai Irigoyen Ceberio, Muhammad Hassan, Albrecht Mayer:
EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge. DATE 2024: 1-6 - [c80]Jihene Bouhlila, Felix Last, Rainer Buchty, Mladen Berekovic, Saleh Mulhem:
Machine Learning for SRAM Stability Analysis. ISCAS 2024: 1-5 - [i8]Wadid Foudhaili, Anouar Nechi, Celine Thermann, Mohammad Al Johmani, Rainer Buchty, Mladen Berekovic, Saleh Mulhem:
Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach. CoRR abs/2404.10792 (2024) - [i7]Mohamed Roshdi, Julian Petzold, Mostafa Wahby, Hussein Ebrahim, Mladen Berekovic, Heiko Hamann:
On the Road to Clarity: Exploring Explainable AI for World Models in a Driver Assistance System. CoRR abs/2404.17350 (2024) - [i6]Saleh Mulhem, Christian Ewert, Andrija Neskovic, Amrit Sharma Poudel, Christoph Hübner, Mladen Berekovic, Rainer Buchty:
Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip. CoRR abs/2410.05109 (2024) - 2023
- [j25]Anouar Nechi, Lukas Groth, Saleh Mulhem, Farhad Merchant, Rainer Buchty, Mladen Berekovic:
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing? ACM Trans. Reconfigurable Technol. Syst. 16(4): 60:1-60:32 (2023) - [c79]Philipp Grothe, Saleh Mulhem, Mladen Berekovic:
An Almost Fully RRAM-Based LUT Design for Reconfigurable Circuits. ARC 2023: 322-337 - [c78]Andrija Neskovic, Saleh Mulhem, Alexander Treff, Rainer Buchty, Thomas Eisenbarth, Mladen Berekovic:
SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not? ICCAD 2023: 1-8 - [c77]Julian Petzold, Mostafa Wahby, Youssef Ziad, Mostafa ElSheikh, Ahmed Dawood, Mladen Berekovic, Heiko Hamann:
Protecting Vulnerable Road Users: Semantic Video Analysis for Accident Prediction. SSCI 2023: 463-469 - [c76]Anouar Nechi, Ahmed Mahmoudi, Christoph Herold, Daniel Widmer, Thomas Kürner, Mladen Berekovic, Saleh Mulhem:
Practical Trustworthiness Model for DNN in Dedicated 6G Application. WiMob 2023: 312-317 - [i5]Anouar Nechi, Ahmed Mahmoudi, Christoph Herold, Daniel Widmer, Thomas Kürner, Mladen Berekovic, Saleh Mulhem:
Practical Trustworthiness Model for DNN in Dedicated 6G Application. CoRR abs/2307.04677 (2023) - [i4]Andrija Neskovic, Saleh Mulhem, Alexander Treff, Rainer Buchty, Thomas Eisenbarth, Mladen Berekovic:
SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not? CoRR abs/2311.13387 (2023) - 2022
- [j24]Bernhard Bauer, Mouadh Ayache, Saleh Mulhem, Meirav Nitzan, Jyotika Athavale, Rainer Buchty, Mladen Berekovic:
On the Dependability Lifecycle of Electrical/Electronic Product Development: The Dual-Cone V-Model. Computer 55(9): 99-106 (2022) - [c75]Christopher Blochwitz, Philipp Grothe, Sven Dreier, Waiel Aljnabi, Rainer Buchty, Mladen Berekovic:
RemEduLa - Remote Education Laboratory for FPGA Design Technology. ISCAS 2022: 1773-1777 - 2021
- [j23]Emad Hamadaqa, Saleh Mulhem, Wael Adi, Mladen Berekovic:
Contemporary Physical Clone-Resistant Identity for IoTs and Emerging Technologies. Cryptogr. 5(4): 32 (2021) - [c74]Christopher Blochwitz, León Philipp, Mladen Berekovic, Thilo Pionteck:
StreamGrid - An AXI-Stream-Compliant Overlay Architecture. ARC 2021: 156-170 - [c73]Randa Zarrouk, Saleh Mulhem, Wael Adi, Mladen Berekovic:
Clone-Resistant Secured Booting Based on Unknown Hashing Created in Self-Reconfigurable Platform. ARC 2021: 203-217 - [c72]Alexander Dörflinger, Mark Albers, Benedikt Kleinbeck, Yejun Guan, Harald Michalik, Raphael Klink, Christopher Blochwitz, Anouar Nechi, Mladen Berekovic:
A comparative survey of open-source application-class RISC-V processor implementations. CF 2021: 12-20 - [c71]Philipp Jungklass, Mladen Berekovic:
Static Allocation of Basic Blocks Based on Runtime and Memory Requirements in Embedded Real-Time Systems with Hierarchical Memory Layout. NG-RES@HiPEAC 2021: 3:1-3:14 - [c70]Christian Böttcher, Philipp Jungklass, Mladen Berekovic:
Hardware-Beschleuniger für automobile Multicore-Mikrocontroller mit einer harten Echtzeitanforderung. Echtzeit 2021: 63-72 - [c69]Sercan Körür, Philipp Jungklass, Mladen Berekovic:
Echtzeitfähige Ethernet-Kommunikation in automobilen Multicore-Systemen mit hierarchischem Speicherlayout. Echtzeit 2021: 83-92
2010 – 2019
- 2019
- [c68]Philipp Jungklass, Mladen Berekovic:
MemOpt: Automated Memory Distribution for Multicore Microcontrollers with Hard Real-Time Requirements. NORCAS 2019: 1-7 - [c67]Philipp Jungklass, Mladen Berekovic:
Cache-Kohärenz für embedded Multicore-Mikrocontroller mit harter Echtzeitanforderung. Echtzeit 2019: 129-138 - 2018
- [c66]Christopher Blochwitz, Julian Wolff, Mladen Berekovic, Dennis Heinrich, Sven Groppe, Jan Moritz Joseph, Thilo Pionteck:
Hardware-Accelerated Index Construction for Semantic Web. FPT 2018: 278-281 - [c65]Philipp Jungklass, Mladen Berekovic:
Effects of Concurrent Access to Embedded Multicore Microcontrollers with Hard Real-Time Demands. SIES 2018: 1-9 - [e6]Mladen Berekovic, Rainer Buchty, Heiko Hamann, Dirk Koch, Thilo Pionteck:
Architecture of Computing Systems - ARCS 2018 - 31st International Conference, Braunschweig, Germany, April 9-12, 2018, Proceedings. Lecture Notes in Computer Science 10793, Springer 2018, ISBN 978-3-319-77609-5 [contents] - 2017
- [c64]Amel Alfahham, Mladen Berekovic:
Energy efficient cooperative spectrum sensing in Cognitive Radio Sensor Network Using FPGA: A survey. FRUCT 2017: 16-25 - [c63]Soenke Michalik, Soeren Michalik, Jamin Naghmouchi, Mladen Berekovic:
Real-time smart stereo camera based on FPGA-SoC. Humanoids 2017: 311-317 - [c62]Luca Mattii, Dragomir Milojevic, Peter Debacker, Yasser Sherazi, Mladen Berekovic, Praveen Raghavan:
IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options. ICCAD 2017: 89-94 - [c61]Patrick Siegl, Rainer Buchty, Mladen Berekovic:
A bandwidth accurate, flexible and rapid simulating multi-HMC modeling tool. MEMSYS 2017: 71-82 - [c60]Haris Isakovic, Radu Grosu, Denise Ratasich, Jiri Kadlec, Zdenek Pohl, Steve Kerrison, Kyriakos Georgiou, Kerstin Eder, Norbert Druml, Lillian Tadros, Flemming Christensen, Emilie Wheatley, Bastian Farkas, Rolf Meyer, Mladen Berekovic:
A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC^2. SAFECOMP Workshops 2017: 127-140 - 2016
- [j22]Rolf Meyer, Jan Wagner, Bastian Farkas, Sven Alexander Horsinka, Patrick Siegl, Rainer Buchty, Mladen Berekovic:
A Scriptable Standard-Compliant Reporting and Logging Framework for SystemC. ACM Trans. Embed. Comput. Syst. 16(1): 6:1-6:28 (2016) - [c59]Patrick Siegl, Rainer Buchty, Mladen Berekovic:
Towards bridging the gap between academic and industrial heterogeneous system architecture design space exploration. RAPIDO@HiPEAC 2016: 4:1-4:6 - [c58]Patrick Siegl, Rainer Buchty, Mladen Berekovic:
Data-Centric Computing Frontiers: A Survey On Processing-In-Memory. MEMSYS 2016: 295-308 - [c57]Syed Abbas Ali Shah, Bastian Farkas, Rolf Meyer, Mladen Berekovic:
Accelerating MPSoC design space exploration within system-level frameworks. NORCAS 2016: 1-6 - 2015
- [c56]Chi-Chia Sun, Heng-Chi Lai, Sin-Kun Lin, Ming-Hwa Sheu, Mladen Berekovic:
High efficient hardware allocation framework of arbitrary inverse transform coding blocks in H.265. ISPACS 2015: 36-39 - [c55]Patrick Siegl, Rainer Buchty, Mladen Berekovic:
Revealing Potential Performance Improvements by Utilizing Hybrid Work-Sharing for Resource-Intensive Seismic Applications. PDP 2015: 659-663 - [c54]Jan Wagner, Rolf Meyer, Rainer Buchty, Mladen Berekovic:
A scriptable, standards-compliant reporting and logging extension for SystemC. SAMOS 2015: 366-371 - [i3]Shaodong Qin, Mladen Berekovic:
A Comparison of High-Level Design Tools for SoC-FPGA on Disparity Map Calculation Example. CoRR abs/1509.00036 (2015) - 2014
- [c53]Hayder Al-Khalissi, Mladen Berekovic, Andrea Marongiu:
On the Relevance of Architectural Awareness for Efficient Fork/Join Support on Cluster-Based Manycores. MES 2014: 9-16 - [c52]Sven Alexander Horsinka, Rolf Meyer, Jan Wagner, Rainer Buchty, Mladen Berekovic:
On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration. NoCArc@MICRO 2014: 39-44 - [c51]Syed Abbas Ali Shah, Jan Wagner, Thomas Schuster, Mladen Berekovic:
A lightweight-system-level power and area estimation methodology for application specific instruction set processors. PATMOS 2014: 1-5 - [c50]Hayder Al-Khalissi, Syed Abbas Ali Shah, Mladen Berekovic:
An Efficient Barrier Implementation for OpenMP-Like Parallelism on the Intel SCC. PDP 2014: 76-83 - [c49]Thomas Schuster, Rolf Meyer, Rainer Buchty, Luca Fossati, Mladen Berekovic:
SoCRocket - A virtual platform for the European Space Agency's SoC development. ReCoSoC 2014: 1-7 - [c48]Ioanna Tsekoura, Gregor Rebel, Peter Glösekötter, Mladen Berekovic:
An evaluation of energy efficient microcontrollers. ReCoSoC 2014: 1-5 - 2013
- [c47]Boris Motruk, Jonas Diemer, Rainer Buchty, Mladen Berekovic:
Power Monitoring for Mixed-Criticality on a Many-Core Platform. ARCS 2013: 13-24 - [c46]Hayder Al-Khalissi, Rainer Buchty, Mladen Berekovic:
Efficient Barrier Synchronization for OpenMP-Like Parallelism on the Intel SCC. ICPADS 2013: 10-17 - [c45]Boris Motruk, Jonas Diemer, Philip Axer, Rainer Buchty, Mladen Berekovic:
Safe Virtual Interrupts Leveraging Distributed Shared Resources and Core-to-Core Communication on Many-Core Platforms. PRDC 2013: 293-302 - [c44]Jan Wagner, Rainer Buchty, Christian Schubert, Mladen Berekovic:
Designing a low-power wireless sensor node rASIP architecture. SiPS 2013: 106-111 - [e5]Mladen Berekovic, Martin Danek:
ARCS 2013 - 26th International Conference on Architecture of Computing Systems 2013, Workshop Proceedings, Feburary 19-22, 2013, Prague, Czech Republic. VDE-Verlag 2013, ISBN 978-3-8007-3492-4 [contents] - 2012
- [j21]Andy D. Pimentel, Naehyuck Chang, Mladen Berekovic:
Introduction to special section ESTIMedia'09. ACM Trans. Embed. Comput. Syst. 11(4): 70:1-70:2 (2012) - [j20]Mladen Berekovic, Samarjit Chakraborty, Petru Eles, Andy D. Pimentel:
Introduction to the Special Section on ESTIMedia'08. ACM Trans. Embed. Comput. Syst. 11(S1): 11 (2012) - [c43]Boris Motruk, Jonas Diemer, Rainer Buchty, Rolf Ernst, Mladen Berekovic:
IDAMC: A Many-Core Platform with Run-Time Monitoring for Mixed-Criticality. HASE 2012: 24-31 - [c42]Hayder Al-Khalissi, Andrea Marongiu, Mladen Berekovic:
Low-Overhead Barrier Synchronization for OpenMP-like Parallelism on the Single-Chip Cloud Computer. MARC@RWTH 2012: 26-31 - 2011
- [c41]Hayder Al-Khalissi, Mladen Berekovic:
Performance of RCCE Broadcast Algorithm in SCC. MARC Symposium 2011: 93-98 - [c40]Matti Bickel, Adrian Knoth, Mladen Berekovic:
Evaluation of Interpreted Languages with Open MPI. EuroMPI 2011: 292-301 - [e4]Mladen Berekovic, William Fornaciari, Uwe Brinkschulte, Cristina Silvano:
Architecture of Computing Systems - ARCS 2011 - 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings. Lecture Notes in Computer Science 6566, Springer 2011, ISBN 978-3-642-19136-7 [contents] - 2010
- [j19]Mladen Berekovic, Andy D. Pimentel:
Editorial. J. Signal Process. Syst. 60(2): 147-148 (2010) - [j18]Matthias Hartmann, Vasileios (Vassilis) Pantazis, Tom Vander Aa, Mladen Berekovic, Christian Hochberger:
Still Image Processing on Coarse-Grained Reconfigurable Array Architectures. J. Signal Process. Syst. 60(2): 225-237 (2010) - [c39]Tim Kranich, Mladen Berekovic:
NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems. DSD 2010: 53-59 - [c38]Dennis Bode, Mladen Berekovic, Axel Borkowski, Ludger Buker:
QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration. DSD 2010: 141-146 - [c37]Jamin Naghmouchi, Daniele Paolo Scarpazza, Mladen Berekovic:
Small-ruleset regular expression matching on GPGPUs: quantitative performance analysis and optimization. ICS 2010: 337-348 - [i2]Matthias Hanke, Tim Kranich, Mladen Berekovic, Yannis Papaefstathiou:
Low-Power Reconfigurable Architectures for High-Performance Mobile Nodes. Dynamically Reconfigurable Architectures 2010
2000 – 2009
- 2009
- [j17]Mladen Berekovic, Vipin Chaudhary, Alex Dean, Jason Fritts:
Editorial. Microprocess. Microsystems 33(4): 233-234 (2009) - [j16]Mladen Berekovic, Andreas Kanstein, Bingfeng Mei, Bjorn De Sutter:
Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor. Microprocess. Microsystems 33(4): 290-294 (2009) - [j15]Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jos Hulzink, Jef L. van Meerbergen:
Design of 100 µW Wireless Sensor Nodes for Biomedical Monitoring. J. Signal Process. Syst. 57(1): 107-119 (2009) - [c36]Andreas Genser, Christian Bachmann, Christian Steger, Jos Hulzink, Mladen Berekovic:
Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing. ASAP 2009: 177-182 - [c35]Christian Bachmann, Andreas Genser, Jos Hulzink, Mladen Berekovic, Christian Steger:
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing. DATE 2009: 1614-1619 - [c34]Mladen Berekovic, Matthias Hanke, Thomas Schuster, Tim Kranich, Rolf Ernst:
ESL design in the context of embedded systems education. WESE@ESWEEK 2009: 13-18 - [e3]Mladen Berekovic, Christian Müller-Schloer, Christian Hochberger, Stephan Wong:
Architecture of Computing Systems - ARCS 2009, 22nd International Conference, Delft, The Netherlands, March 10-13, 2009. Proceedings. Lecture Notes in Computer Science 5455, Springer 2009, ISBN 978-3-642-00453-7 [contents] - 2008
- [j14]Mladen Berekovic, Christian Hochberger, Andreas Koch:
Rekonfigurierbare Architekturen. Inform. Spektrum 31(4): 344-347 (2008) - [j13]Mladen Berekovic, Andy D. Pimentel, Timo D. Hämäläinen:
Editorial. J. Syst. Archit. 54(11): 1017-1018 (2008) - [j12]Mladen Berekovic, Tim Niggemeier:
A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance. J. Signal Process. Syst. 50(2): 201-229 (2008) - [c33]Andres Garcia, Mladen Berekovic, Tom Vander Aa:
Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor. ASAP 2008: 245-250 - [c32]Frederico Pratas, Georgi Gaydadjiev, Mladen Berekovic, Leonel Sousa, Stefanos Kaxiras:
Low power microarchitecture with instruction reuse. Conf. Computing Frontiers 2008: 149-158 - [c31]Frank Bouwens, Mladen Berekovic, Bjorn De Sutter, Georgi Gaydadjiev:
Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array. HiPEAC 2008: 66-81 - [c30]Jochem Govers, Jos Huisken, Mladen Berekovic, Olivier Rousseaux, Frank Bouwens, Michael De Nil, Jef L. van Meerbergen:
Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP. HiPEAC 2008: 82-96 - [c29]Mladen Berekovic, Frank Bouwens, Tom Vander Aa, Diederik Verkest:
Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor. PATMOS 2008: 449-457 - [e2]Mladen Berekovic, Nikitas J. Dimopoulos, Stephan Wong:
Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings. Lecture Notes in Computer Science 5114, Springer 2008, ISBN 978-3-540-70549-9 [contents] - 2007
- [c28]Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev:
Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array. ARC 2007: 1-13 - [c27]Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Berekovic:
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture. ARC 2007: 26-38 - [c26]C. Arbelo, Andreas Kanstein, Sebastián López, José Francisco López, Mladen Berekovic, Roberto Sarmiento, Jean-Yves Mignolet:
Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter. DATE 2007: 177-182 - [c25]Mladen Berekovic:
Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical Monitoring. DSD 2007: 16-18 - [c24]Matthias Hartmann, Vasileios (Vassilis) Pantazis, Tom Vander Aa, Mladen Berekovic, Christian Hochberger, Bjorn De Sutter:
Still Image Processing on Coarse-Grained Reconfigurable Array Architectures. ESTIMedia 2007: 67-72 - [c23]Michael De Nil, Lennart Yseboodt, Frank Bouwens, Jos Hulzink, Mladen Berekovic, Jos Huisken, Jef L. van Meerbergen:
Ultra Low Power ASIP Design for Wireless Sensor Nodes. ICECS 2007: 1352-1355 - [c22]Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jef L. van Meerbergen:
Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring. SAMOS 2007: 385-395 - [e1]Stamatis Vassiliadis, Mladen Berekovic, Timo D. Hämäläinen:
Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings. Lecture Notes in Computer Science 4599, Springer 2007, ISBN 978-3-540-73622-6 [contents] - [i1]Lennart Yseboodt, Michael De Nil, Mladen Berekovic:
Electrocardiogram on Wireless Sensor Nodes. Power-aware Computing Systems 2007 - 2006
- [c21]Bjorn De Sutter, Bingfeng Mei, T. Andrei Bartic, Tom Vander Aa, Mladen Berekovic, Jean-Yves Mignolet, Kris Croes, Paul Coene, Miro Cupac, Aïssa Couvreur, Andy Folens, Steven Dupont, Bert Van Thielen, Andreas Kanstein, Hong-Seok Kim, Sukjin Kim:
Hardware and a Tool Chain for ADRES. ARC 2006: 425-430 - [c20]Mladen Berekovic, Tim Niggemeier:
A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme. SAMOS 2006: 289-298 - [c19]Julien Penders, Bert Gyselinckx, Ruud J. M. Vullers, Olivier Rousseaux, Mladen Berekovic, Michael De Nil, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov:
Human++: Emerging Technology for Body Area Networks. VLSI-SoC (Selected Papers) 2006: 377-397 - 2005
- [b1]Mladen Berekovic:
Eine skalierbare, verteilte Prozessor-Architektur mit simultanem multi-threading für Anwendungen der digitalen Signalverarbeitung. University of Hanover, 2005, ISBN 3-18-337709-8, pp. 1-195 - [j11]Hans-Joachim Stolberg, Mladen Berekovic, Sören Moch, Lars Friebe, Mark Bernd Kulaczewski, Sebastian Flügel, Heiko Klußmann, Andreas Dehnhardt, Peter Pirsch:
HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing. J. VLSI Signal Process. 41(1): 9-20 (2005) - [j10]Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch:
A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications. J. VLSI Signal Process. 41(2): 139-151 (2005) - 2004
- [j9]Sören Moch, Mladen Berekovic, Hans-Joachim Stolberg, Lars Friebe, Mark Bernd Kulaczewski, Andreas Dehnhardt, Peter Pirsch:
HIBRID-SOC: a multi-core architecture for image and video applications. SIGARCH Comput. Archit. News 32(3): 55-61 (2004) - [j8]Mladen Berekovic, Sören Moch, Peter Pirsch:
A scalable, clustered SMT processor for digital signal processing. SIGARCH Comput. Archit. News 32(3): 62-69 (2004) - 2003
- [c18]Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Xun Mao, Mark Bernd Kulaczewski, Heiko Klußmann, Peter Pirsch:
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications. DATE 2003: 20008-20013 - [c17]Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Mark Bernd Kulaczewski, Peter Pirsch:
HiBRID-SoC: a multi-core architecture for image and video applications. ICIP (3) 2003: 101-104 - [c16]Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Mark Bernd Kulaczewski, Peter Pirsch:
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing. VLSI-SOC 2003: 155-160 - 2002
- [j7]Mladen Berekovic, Hans-Joachim Stolberg, Peter Pirsch:
Multicore system-on-chip architecture for MPEG-4 streaming video. IEEE Trans. Circuits Syst. Video Technol. 12(8): 688-699 (2002) - [j6]Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo:
Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing. J. VLSI Signal Process. 31(2): 157-171 (2002) - [c15]Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch:
A platform-independent methodology for performance estimation of streaming media applications. ICME (2) 2002: 105-108 - 2001
- [c14]Mladen Berekovic, Hans-Joachim Stolberg, Peter Pirsch, Holger Runge:
A programmable co-porcessor for MPEG-4 video. ICASSP 2001: 1021-1024 - [c13]Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch, Holger Runge:
Implementing The MPEG-4 Advanced Simple Profile For Streaming Video Applications. ICME 2001 - 2000
- [c12]Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo:
Architecture of an Image Rendering Co-Processor for MPEG-4 Systems. ASAP 2000: 15-24 - [c11]Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo:
Co-processor architecture for MPEG-4 main profile visual compositing. ISCAS 2000: 180-183 - [c10]Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch, Holger Runge, Henning Möller, Johannes Kneip:
The M-PIRE MPEG-4 codec DSP and its macroblock engine. ISCAS 2000: 192-195 - [c9]Christoph Heer, Carolina Miro, Anne Lafage, Mladen Berekovic, Giovanni Ghigo, Thorsten Selinger, Kai-Immo Wels:
Coprocessor architecture for MPEG-4 video object rendering. VCIP 2000: 1451-1458
1990 – 1999
- 1999
- [j5]Mladen Berekovic, Helge Kloos, Peter Pirsch:
Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications. J. VLSI Signal Process. 22(1): 31-43 (1999) - [j4]S. Bauer, Johannes Kneip, T. Mlasko, Bernd Schmale, J. Vollmer, Andreas Hutter, Mladen Berekovic:
The MPEG-4 Multimedia Coding Standard: Algorithms, Architectures and Applications. J. VLSI Signal Process. 23(1): 7-26 (1999) - [j3]Mladen Berekovic, Hans-Joachim Stolberg, Mark Bernd Kulaczewski, Peter Pirsch, Henning Möller, Holger Runge, Johannes Kneip, Benno Stabernack:
Instruction Set Extensions for MPEG-4 Video. J. VLSI Signal Process. 23(1): 27-49 (1999) - [c8]Helge Kloos, Mladen Berekovic, Peter Pirsch:
Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen. ARCS 1999: 5-14 - [c7]Christoph Heer, Carolina Miro, Anne Lafage, Mladen Berekovic, Giovanni Ghigo, Thorsten Selinger, Kai-Immo Wels:
Design and architecture of the MPEG-4 video rendering co-processor 'TANGRAM'. ICECS 1999: 1205-1210 - [c6]Mladen Berekovic, K. Jacob, Peter Pirsch:
Architecture of a hardware module for MPEG-4 shape decoding. ISCAS (1) 1999: 157-160 - 1998
- [j2]Mladen Berekovic, Peter Pirsch, Johannes Kneip:
An Algorithm-Hardware-System Approach to VLIW Multimedia Processors. J. VLSI Signal Process. 20(1-2): 163-180 (1998) - [c5]Mladen Berekovic, Peter Pirsch:
An Array Processor Architecture with Parallel Data Cache for Image Rendering and Compositing. Computer Graphics International 1998: 411- - [c4]Jens Peter Wittenburg, Willm Hinrichs, Johannes Kneip, Martin Ohmacht, Mladen Berekovic, Hanno Lieske, Helge Kloos, Peter Pirsch:
Realization of a Programmable Parallel DSP for High Performance Image Processing Applications. DAC 1998: 56-61 - [c3]Mladen Berekovic, Rainer Frase, Peter Pirsch:
A flexible processor architecture for MPEG-4 image compositing. ICASSP 1998: 3153-3156 - [c2]Mladen Berekovic, Peter Pirsch:
Architecture of a coprocessor module for image compositing. ICECS 1998: 203-206 - 1997
- [j1]Johannes Kneip, Mladen Berekovic, Jens Peter Wittenburg, Willm Hinrichs, Peter Pirsch:
An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor. J. VLSI Signal Process. 16(1): 31-40 (1997) - [c1]Johannes Kneip, Mladen Berekovic, Peter Pirsch:
An algorithm-hardware-system approach to VLIW multimedia processors. MMSP 1997: 433-438
Coauthor Index
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