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Provider: Schloss Dagstuhl - Leibniz Center for Informatics Database: dblp computer science bibliography Content:text/plain; charset="utf-8" TY - JOUR ID - DBLP:journals/jpdc/CajahuaringaZRY24 AU - Cajahuaringa, Samuel AU - Zanotto, Leandro N. AU - Rigo, Sandro AU - Yviquel, Hervé AU - Skaf, Munir S. AU - Araujo, Guido TI - Ion-molecule collision cross-section calculations using trajectory parallelization in distributed systems. JO - J. Parallel Distributed Comput. VL - 191 SP - 104902 PY - 2024// DO - 10.1016/J.JPDC.2024.104902 UR - https://doi.org/10.1016/j.jpdc.2024.104902 ER - TY - JOUR ID - DBLP:journals/tc/MoraisAJRAFGM24 AU - Morais, Lucas AU - Álvarez, Carlos AU - Jiménez-González, Daniel AU - Ruiz, Juan Miguel De Haro AU - Araujo, Guido AU - Frank, Michael AU - Goldman, Alfredo AU - Martorell, Xavier TI - Enabling HW-Based Task Scheduling in Large Multicore Architectures. JO - IEEE Trans. Computers VL - 73 IS - 1 SP - 138 EP - 151 PY - 2024/01/ DO - 10.1109/TC.2023.3323781 UR - https://doi.org/10.1109/TC.2023.3323781 ER - TY - CPAPER ID - DBLP:conf/europar/MaltempiRPYCA24 AU - Maltempi, Thiago AU - Rigo, Sandro AU - Pereira, Márcio Machado AU - Yviquel, Hervé AU - Costa, Jessé AU - Araujo, Guido TI - Combining Compression and Prefetching to Improve Checkpointing for Inverse Seismic Problems in GPUs. BT - Euro-Par 2024: Parallel Processing - 30th European Conference on Parallel and Distributed Processing, Madrid, Spain, August 26-30, 2024, Proceedings, Part III SP - 167 EP - 181 PY - 2024// DO - 10.1007/978-3-031-69583-4_12 UR - https://doi.org/10.1007/978-3-031-69583-4_12 ER - TY - CPAPER ID - DBLP:conf/iwomp/RossoPLPRYBFA24 AU - Rosso, Pedro Henrique Di Francia AU - Petrica, Lucian AU - Lisa, Nusrat Jahan AU - Pereira, Márcio Machado AU - Rigo, Sandro AU - Yviquel, Hervé AU - Bonato, Vanderlei AU - Francesquini, Emilio AU - Araujo, Guido TI - Integrating Multi-FPGA Acceleration to OpenMP Distributed Computing. BT - Advancing OpenMP for Future Accelerators - 20th International Workshop on OpenMP, IWOMP 2024, Perth, WA, Australia, September 23-25, 2024, Proceedings SP - 49 EP - 63 PY - 2024// DO - 10.1007/978-3-031-72567-8_4 UR - https://doi.org/10.1007/978-3-031-72567-8_4 ER - TY - Informal or Other Publication ID - DBLP:journals/corr/abs-2407-10730 AU - Alvarenga, Lucas AU - Ferrari, Victor AU - Souza, Rafael AU - Pereira, Márcio Machado AU - Araujo, Guido TI - ConvBench: A Comprehensive Benchmark for 2D Convolution Primitive Evaluation. JO - CoRR VL - abs/2407.10730 PY - 2024// DO - 10.48550/ARXIV.2407.10730 UR - https://doi.org/10.48550/arXiv.2407.10730 ER - TY - JOUR ID - DBLP:journals/jcisd/CajahuaringaCZAS23 AU - Cajahuaringa, Samuel AU - Caetano, Daniel L. Z. AU - Zanotto, Leandro N. AU - Araujo, Guido AU - Skaf, Munir S. TI - MassCCS: A High-Performance Collision Cross-Section Software for Large Macromolecular Assemblies. JO - J. Chem. Inf. Model. VL - 63 IS - 11 SP - 3557 EP - 3566 PY - 2023/06/ DO - 10.1021/ACS.JCIM.3C00405 UR - https://doi.org/10.1021/acs.jcim.3c00405 ER - TY - JOUR ID - DBLP:journals/jpdc/MoralesHCBA23 AU - Morales, Catalina Munoz AU - Honorio, Bruno C. AU - Carvalho, Joao P. L. de AU - Baldassin, Alexandro AU - Araujo, Guido TI - On the impact of mode transition on phased transactional memory performance. JO - J. Parallel Distributed Comput. VL - 173 SP - 126 EP - 139 PY - 2023/03/ DO - 10.1016/J.JPDC.2022.11.009 UR - https://doi.org/10.1016/j.jpdc.2022.11.009 ER - TY - JOUR ID - DBLP:journals/jpdc/SousaPKKJKFA23 AU - Sousa, Rafael C. F. AU - Pereira, Márcio Machado AU - Kwon, Yongin AU - Kim, Taeho AU - Jung, Namsoon AU - Kim, Chang Soo AU - Frank, Michael AU - Araujo, Guido TI - Tensor slicing and optimization for multicore NPUs. JO - J. Parallel Distributed Comput. VL - 175 SP - 66 EP - 79 PY - 2023/05/ DO - 10.1016/J.JPDC.2022.12.008 UR - https://doi.org/10.1016/j.jpdc.2022.12.008 ER - TY - JOUR ID - DBLP:journals/spe/KuzmaKCMBAA23 AU - Kuzma, Braedy AU - Korostelev, Ivan AU - Carvalho, João P. L. de AU - Moreira, José E. AU - Barton, Christopher AU - Araujo, Guido AU - Amaral, José Nelson TI - Fast matrix multiplication via compiler-only layered data reorganization and intrinsic lowering. JO - Softw. Pract. Exp. VL - 53 IS - 9 SP - 1793 EP - 1814 PY - 2023/09/ DO - 10.1002/SPE.3214 UR - https://doi.org/10.1002/spe.3214 ER - TY - JOUR ID - DBLP:journals/taco/EspindolaZYA23 AU - Espindola, Vinicius AU - Zago, Luciano G. AU - Yviquel, Hervé AU - Araujo, Guido TI - Source Matching and Rewriting for MLIR Using String-Based Automata. JO - ACM Trans. Archit. Code Optim. VL - 20 IS - 2 SP - 22:1 EP - 22:26 PY - 2023/06/ DO - 10.1145/3571283 UR - https://doi.org/10.1145/3571283 ER - TY - JOUR ID - DBLP:journals/taco/FerrariSPCAMA23 AU - Ferrari, Victor AU - Sousa, Rafael Cardoso Fernandes AU - Pereira, Márcio Machado AU - Carvalho, Joao P. L. de AU - Amaral, José Nelson AU - Moreira, José E. AU - Araujo, Guido TI - Advancing Direct Convolution Using Convolution Slicing Optimization and ISA Extensions. JO - ACM Trans. Archit. Code Optim. VL - 20 IS - 4 SP - 54:1 EP - 54:26 PY - 2023/12/ DO - 10.1145/3625004 UR - https://doi.org/10.1145/3625004 ER - TY - Informal or Other Publication ID - DBLP:journals/corr/abs-2303-04739 AU - Ferrari, Victor AU - Sousa, Rafael C. F. AU - Pereira, Márcio Machado AU - Carvalho, João P. L. de AU - Amaral, José Nelson AU - Moreira, José E. AU - Araujo, Guido TI - Advancing Direct Convolution using Convolution Slicing Optimization and ISA Extensions. JO - CoRR VL - abs/2303.04739 PY - 2023// DO - 10.48550/ARXIV.2303.04739 UR - https://doi.org/10.48550/arXiv.2303.04739 ER - TY - Informal or Other Publication ID - DBLP:journals/corr/abs-2304-03013 AU - Sousa, Rafael C. F. AU - Pereira, Márcio Machado AU - Kwon, Yongin AU - Kim, Taeho AU - Jung, Namsoon AU - Kim, Chang Soo AU - Frank, Michael AU - Araujo, Guido TI - Tensor Slicing and Optimization for Multicore NPUs. JO - CoRR VL - abs/2304.03013 PY - 2023// DO - 10.48550/ARXIV.2304.03013 UR - https://doi.org/10.48550/arXiv.2304.03013 ER - TY - Informal or Other Publication ID - DBLP:journals/corr/abs-2305-18236 AU - Kuzma, Braedy AU - Korostelev, Ivan AU - Carvalho, João P. L. de AU - Moreira, José E. AU - Barton, Christopher AU - Araujo, Guido AU - Amaral, José Nelson TI - Fast Matrix Multiplication via Compiler-only Layered Data Reorganization and Intrinsic Lowering. JO - CoRR VL - abs/2305.18236 PY - 2023// DO - 10.48550/ARXIV.2305.18236 UR - https://doi.org/10.48550/arXiv.2305.18236 ER - TY - JOUR ID - DBLP:journals/micro/AraujoW22 AU - Araujo, Guido AU - Wanner, Lucas TI - Special Issue on Compiling for Accelerators. JO - IEEE Micro VL - 42 IS - 5 SP - 6 EP - 8 PY - 2022// DO - 10.1109/MM.2022.3193765 UR - https://doi.org/10.1109/MM.2022.3193765 ER - TY - JOUR ID - DBLP:journals/taco/HonorioCMBA22 AU - Honorio, Bruno Chinelato AU - Carvalho, João P. L. de AU - Morales, Catalina Munoz AU - Baldassin, Alexandro AU - Araujo, Guido TI - Using Barrier Elision to Improve Transactional Code Generation. JO - ACM Trans. Archit. Code Optim. VL - 19 IS - 3 SP - 46:1 EP - 46:23 PY - 2022// DO - 10.1145/3533318 UR - https://doi.org/10.1145/3533318 ER - TY - CPAPER ID - DBLP:conf/IEEEpact/FerrariSPCAA22 AU - Ferrari, Victor AU - Sousa, Rafael C. F. AU - Pereira, Márcio Machado AU - Carvalho, João P. L. de AU - Amaral, José Nelson AU - Araujo, Guido TI - Improving Convolution via Cache Hierarchy Tiling and Reduced Packing. BT - Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, PACT 2022, Chicago, Illinois, October 8-12, 2022 SP - 538 EP - 539 PY - 2022// DO - 10.1145/3559009.3569678 UR - https://doi.org/10.1145/3559009.3569678 ER - TY - CPAPER ID - DBLP:conf/icppw/YviquelPFVLRCCD22 AU - Yviquel, Hervé AU - Pereira, Márcio Machado AU - Francesquini, Emilio AU - Valarini, Guilherme AU - Leite, Gustavo AU - Rosso, Pedro Henrique Di Francia AU - Ceccato, Rodrigo AU - Cusihualpa, Carla AU - Dias, Vitoria AU - Rigo, Sandro AU - Souza, Alan AU - Araujo, Guido TI - The OpenMP Cluster Programming Model. BT - Workshop Proceedings of the 51st International Conference on Parallel Processing, ICPP Workshops 2022, Bordeaux, France, 29 August 2022 - 1 September 2022 SP - 17:1 EP - 17:11 PY - 2022// DO - 10.1145/3547276.3548444 UR - https://doi.org/10.1145/3547276.3548444 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/CardosoYVLCPSA22 AU - Cardoso, Carla AU - Yviquel, Hervé AU - Valarini, Guilherme AU - Leite, Gustavo AU - Ceccato, Rodrigo AU - Pereira, Márcio Machado AU - Souza, Alan AU - Araujo, Guido TI - An OpenMP-only Linear Algebra Library for Distributed Architectures. BT - International Symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PADW 2022, Bordeaux, France, November 2-5, 2022 SP - 17 EP - 24 PY - 2022// DO - 10.1109/SBAC-PADW56527.2022.00013 UR - https://doi.org/10.1109/SBAC-PADW56527.2022.00013 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/CeccatoYPSA22 AU - Ceccato, Rodrigo AU - Yviquel, Hervé AU - Pereira, Márcio Machado AU - Souza, Alan AU - Araujo, Guido TI - Implementing the Broadcast Operation in a Distributed Task-based Runtime. BT - International Symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PADW 2022, Bordeaux, France, November 2-5, 2022 SP - 25 EP - 32 PY - 2022// DO - 10.1109/SBAC-PADW56527.2022.00014 UR - https://doi.org/10.1109/SBAC-PADW56527.2022.00014 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/CajahuaringaZCR22 AU - Cajahuaringa, Samuel AU - Zanotto, Leandro N. AU - Caetano, Daniel L. Z. AU - Rigo, Sandro AU - Yviquel, Hervé AU - Skaf, Munir S. AU - Araujo, Guido TI - Ion-Molecule Collision Cross-Section Simulation using Linked-cell and Trajectory Parallelization. BT - 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Bordeaux, France, November 2-5, 2022 SP - 150 EP - 159 PY - 2022// DO - 10.1109/SBAC-PAD55451.2022.00026 UR - https://doi.org/10.1109/SBAC-PAD55451.2022.00026 ER - TY - Informal or Other Publication ID - DBLP:journals/corr/abs-2202-04153 AU - Couto, Vinicius AU - Zago, Luciano G. AU - Yviquel, Hervé AU - Araújo, Guido TI - Source Matching and Rewriting. JO - CoRR VL - abs/2202.04153 PY - 2022// UR - https://arxiv.org/abs/2202.04153 ER - TY - Informal or Other Publication ID - DBLP:journals/corr/abs-2207-05677 AU - Yviquel, Hervé AU - Pereira, Márcio Machado AU - Francesquini, Emilio AU - Valarini, Guilherme AU - Leite, Gustavo AU - Rosso, Pedro Henrique Di Francia AU - Ceccato, Rodrigo AU - Cusihualpa, Carla AU - Dias, Vitoria AU - Rigo, Sandro AU - Souza, Alan AU - Araujo, Guido TI - The OpenMP Cluster Programming Model. JO - CoRR VL - abs/2207.05677 PY - 2022// DO - 10.48550/ARXIV.2207.05677 UR - https://doi.org/10.48550/arXiv.2207.05677 ER - TY - JOUR ID - DBLP:journals/taco/CarvalhoKKABMA21 AU - Carvalho, João P. L. de AU - Kuzma, Braedy AU - Korostelev, Ivan AU - Amaral, José Nelson AU - Barton, Christopher AU - Moreira, José E. AU - Araujo, Guido TI - KernelFaRer: Replacing Native-Code Idioms with High-Performance Library Calls. JO - ACM Trans. Archit. Code Optim. VL - 18 IS - 3 SP - 38:1 EP - 38:22 PY - 2021// DO - 10.1145/3459010 UR - https://doi.org/10.1145/3459010 ER - TY - CPAPER ID - DBLP:conf/europar/MoralesMCHBA21 AU - Morales, Catalina Munoz AU - Murari, Rafael AU - Carvalho, Joao P. L. de AU - Honorio, Bruno Chinelato AU - Baldassin, Alexandro AU - Araujo, Guido TI - Accelerating Graph Applications Using Phased Transactional Memory. BT - Euro-Par 2021: Parallel Processing - 27th International Conference on Parallel and Distributed Computing, Lisbon, Portugal, September 1-3, 2021, Proceedings SP - 421 EP - 434 PY - 2021// DO - 10.1007/978-3-030-85665-6_26 UR - https://doi.org/10.1007/978-3-030-85665-6_26 ER - TY - CPAPER ID - DBLP:conf/fccm/NepomucenoSVPYA21 AU - Nepomuceno, Ramon AU - Sterle, Renan AU - Valarini, Guilherme AU - Pereira, Márcio Machado AU - Yviquel, Hervé AU - Araujo, Guido TI - Enabling OpenMP Task Parallelism on Multi-FPGAs. BT - 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2021, Orlando, FL, USA, May 9-12, 2021 SP - 260 PY - 2021// DO - 10.1109/FCCM51124.2021.00047 UR - https://doi.org/10.1109/FCCM51124.2021.00047 ER - TY - CPAPER ID - DBLP:conf/ipps/RohwedderCAACW21 AU - Rohwedder, Caio S. AU - Carvalho, João P. L. de AU - Amaral, José Nelson AU - Araújo, Guido AU - Colmenares, Giancarlo AU - Wang, Kai-Ting Amy TI - Pooling Acceleration in the DaVinci Architecture Using Im2col and Col2im Instructions. BT - IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPS Workshops 2021, Portland, OR, USA, June 17-21, 2021 SP - 46 EP - 55 PY - 2021// DO - 10.1109/IPDPSW52791.2021.00016 UR - https://doi.org/10.1109/IPDPSW52791.2021.00016 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/MoralesHBA21 AU - Morales, Catalina Munoz AU - Honorio, Bruno C. AU - Baldassin, Alexandro AU - Araujo, Guido TI - Improving Phased Transactional Memory via Commit Throughput and Capacity Estimation. BT - 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2021, Belo Horizonte, Brazil, October 26-29, 2021 SP - 44 EP - 53 PY - 2021// DO - 10.1109/SBAC-PAD53543.2021.00016 UR - https://doi.org/10.1109/SBAC-PAD53543.2021.00016 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/SousaJKFA21 AU - Sousa, Rafael C. F. AU - Jung, Byungmin AU - Kwak, Jaehwa AU - Frank, Michael AU - Araujo, Guido TI - Efficient Tensor Slicing for Multicore NPUs using Memory Burst Modeling. BT - 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2021, Belo Horizonte, Brazil, October 26-29, 2021 SP - 84 EP - 93 PY - 2021// DO - 10.1109/SBAC-PAD53543.2021.00020 UR - https://doi.org/10.1109/SBAC-PAD53543.2021.00020 ER - TY - Informal or Other Publication ID - DBLP:journals/corr/abs-2103-10573 AU - Nepomuceno, Ramon AU - Sterle, Renan AU - Valarini, Guilherme AU - Pereira, Márcio Machado AU - Yviquel, Hervé AU - Araujo, Guido TI - Enabling OpenMP Task Parallelism on Multi-FPGAs. JO - CoRR VL - abs/2103.10573 PY - 2021// UR - https://arxiv.org/abs/2103.10573 ER - TY - CPAPER ID - DBLP:conf/europar/BaldassinMCAC0020 AU - Baldassin, Alexandro AU - Murari, Rafael AU - Carvalho, João P. L. de AU - Araujo, Guido AU - Castro, Daniel AU - Barreto, João AU - Romano, Paolo TI - NV-PhTM: An Efficient Phase-Based Transactional System for Non-volatile Memory. BT - Euro-Par 2020: Parallel Processing - 26th International Conference on Parallel and Distributed Computing, Warsaw, Poland, August 24-28, 2020, Proceedings SP - 477 EP - 492 PY - 2020// DO - 10.1007/978-3-030-57675-2_30 UR - https://doi.org/10.1007/978-3-030-57675-2_30 ER - TY - CPAPER ID - DBLP:conf/ipps/CarvalhoHBA20 AU - Carvalho, João P. L. de AU - Honorio, Bruno C. AU - Baldassin, Alexandro AU - Araujo, Guido TI - Improving Transactional Code Generation via Variable Annotation and Barrier Elision. BT - 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), New Orleans, LA, USA, May 18-22, 2020 SP - 1008 EP - 1017 PY - 2020// DO - 10.1109/IPDPS47924.2020.00107 UR - https://doi.org/10.1109/IPDPS47924.2020.00107 ER - TY - CPAPER ID - DBLP:conf/iwomp/HonorioCSA20 AU - Honorio, Bruno Chinelato AU - Carvalho, João P. L. de AU - Skaf, Munir S. AU - Araujo, Guido TI - Using OpenMP to Detect and Speculate Dynamic DOALL Loops. BT - OpenMP: Portable Multi-Level Parallelism on Modern Systems - 16th International Workshop on OpenMP, IWOMP 2020, Austin, TX, USA, September 22-24, 2020, Proceedings SP - 231 EP - 246 PY - 2020// DO - 10.1007/978-3-030-58144-2_15 UR - https://doi.org/10.1007/978-3-030-58144-2_15 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/PinhoYPA20 AU - Pinho, Vitoria AU - Yviquel, Hervé AU - Pereira, Márcio Machado AU - Araujo, Guido TI - OmpTracing: Easy Profiling of OpenMP Programs. BT - 32nd IEEE International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2020, Porto, Portugal, September 9-11, 2020 SP - 249 EP - 256 PY - 2020// DO - 10.1109/SBAC-PAD49847.2020.00042 UR - https://doi.org/10.1109/SBAC-PAD49847.2020.00042 ER - TY - CPAPER ID - DBLP:conf/wosp/CarvalhoKA20 AU - Carvalho, João P. L. de AU - Kuzma, Braedy AU - Araujo, Guido TI - Acceleration Opportunities in Linear Algebra Applications via Idiom Recognition. BT - Companion of the 2020 ACM/SPEC International Conference on Performance Engineering, ICPE 2020, Edmonton, AB, Canada, April 20-24, 2020 SP - 34 EP - 35 PY - 2020// DO - 10.1145/3375555.3383586 UR - https://doi.org/10.1145/3375555.3383586 ER - TY - JOUR ID - DBLP:journals/jpdc/SousaPPA19 AU - Sousa, Rafael C. F. AU - Pereira, Márcio Machado AU - Pereira, Fernando Magno Quintão AU - Araujo, Guido TI - Data-flow analysis and optimization for data coherence in heterogeneous architectures. JO - J. Parallel Distributed Comput. VL - 130 SP - 126 EP - 139 PY - 2019// DO - 10.1016/J.JPDC.2019.04.004 UR - https://doi.org/10.1016/j.jpdc.2019.04.004 ER - TY - JOUR ID - DBLP:journals/tpds/CarvalhoAB19 AU - Carvalho, Joao P. L. de AU - Araujo, Guido AU - Baldassin, Alexandro TI - The Case for Phase-Based Transactional Memory. JO - IEEE Trans. Parallel Distributed Syst. VL - 30 IS - 2 SP - 459 EP - 472 PY - 2019// DO - 10.1109/TPDS.2018.2861712 UR - https://doi.org/10.1109/TPDS.2018.2861712 UR - http://doi.ieeecomputersociety.org/10.1109/TPDS.2018.2861712 ER - TY - CPAPER ID - DBLP:conf/dsd/HoffmanGACA19 AU - Hoffman, Caio AU - Gebotys, Catherine H. AU - Aranha, Diego F. AU - Côrtes, Mario Lúcio AU - Araújo, Guido TI - Circumventing Uniqueness of XOR Arbiter PUFs. BT - 22nd Euromicro Conference on Digital System Design, DSD 2019, Kallithea, Greece, August 28-30, 2019 SP - 222 EP - 229 PY - 2019// DO - 10.1109/DSD.2019.00041 UR - https://doi.org/10.1109/DSD.2019.00041 ER - TY - CPAPER ID - DBLP:conf/micro/MoraisSG0BFA19 AU - Morais, Lucas AU - Silva, Vitor AU - Goldman, Alfredo AU - Álvarez, Carlos AU - Bosch, Jaume AU - Frank, Michael AU - Araujo, Guido TI - Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor. BT - Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2019, Columbus, OH, USA, October 12-16, 2019. SP - 861 EP - 872 PY - 2019// DO - 10.1145/3352460.3358271 UR - https://doi.org/10.1145/3352460.3358271 ER - TY - JOUR ID - DBLP:journals/jcc/ZanottoHSAS18 AU - Zanotto, Leandro AU - Heerdt, Gabriel AU - Souza, Paulo C. T. AU - Araujo, Guido AU - Skaf, Munir S. TI - High performance collision cross section calculation - HPCCS. JO - J. Comput. Chem. VL - 39 IS - 21 SP - 1675 EP - 1681 PY - 2018// DO - 10.1002/JCC.25199 UR - https://doi.org/10.1002/jcc.25199 UR - https://www.wikidata.org/entity/Q87934903 ER - TY - JOUR ID - DBLP:journals/mam/SuritaCAA18 AU - Surita, Rodrigo C. AU - Côrtes, Mario Lúcio AU - Aranha, Diego F. AU - Araujo, Guido TI - CRPUF: A modeling-resistant delay PUF based on cylindrical reconvergence. JO - Microprocess. Microsystems VL - 60 SP - 185 EP - 195 PY - 2018// DO - 10.1016/J.MICPRO.2018.05.006 UR - https://doi.org/10.1016/j.micpro.2018.05.006 UR - https://www.wikidata.org/entity/Q59755088 ER - TY - JOUR ID - DBLP:journals/taco/YviquelCA18 AU - Yviquel, Hervé AU - Cruz, Lauro AU - Araujo, Guido TI - Cluster Programming using the OpenMP Accelerator Model. JO - ACM Trans. Archit. Code Optim. VL - 15 IS - 3 SP - 35:1 EP - 35:23 PY - 2018// DO - 10.1145/3226112 UR - https://doi.org/10.1145/3226112 ER - TY - JOUR ID - DBLP:journals/tpds/SalamancaAA18 AU - Salamanca, Juan AU - Amaral, José Nelson AU - Araujo, Guido TI - Using Hardware-Transactional-Memory Support to Implement Thread-Level Speculation. JO - IEEE Trans. Parallel Distributed Syst. VL - 29 IS - 2 SP - 466 EP - 480 PY - 2018// DO - 10.1109/TPDS.2017.2752169 UR - https://doi.org/10.1109/TPDS.2017.2752169 UR - http://doi.ieeecomputersociety.org/10.1109/TPDS.2017.2752169 ER - TY - CPAPER ID - DBLP:conf/IEEEpact/RamosMSAP18 AU - Ramos, Pedro AU - Mendonca, Gleison Souza Diniz AU - Soares, Divino AU - Araújo, Guido AU - Pereira, Fernando Magno Quintão TI - Automatic annotation of tasks in structured code. BT - Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, PACT 2018, Limassol, Cyprus, November 01-04, 2018 SP - 31:1 EP - 31:13 PY - 2018// DO - 10.1145/3243176.3243200 UR - https://doi.org/10.1145/3243176.3243200 ER - TY - CPAPER ID - DBLP:conf/fccm/CeisslerNPA18 AU - Ceissler, Ciro AU - Nepomuceno, Ramon AU - Pereira, Márcio Machado AU - Araujo, Guido TI - Automatic Offloading of Cluster Accelerators. BT - 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018, Boulder, CO, USA, April 29 - May 1, 2018 SP - 224 PY - 2018// DO - 10.1109/FCCM.2018.00058 UR - https://doi.org/10.1109/FCCM.2018.00058 UR - https://doi.ieeecomputersociety.org/10.1109/FCCM.2018.00058 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/MattosLSCPA18 AU - Mattos, Luis AU - Lucas, Divino Cesar S. AU - Salamanca, Juan AU - Carvalho, Joao P. L. de AU - Pereira, Márcio Machado AU - Araujo, Guido TI - DOACROSS Parallelization Based on Component Annotation and Loop-Carried Probability. BT - 30th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2018, Lyon, France, September 24-27, 2018 SP - 29 EP - 32 PY - 2018// DO - 10.1109/CAHPC.2018.8645904 UR - https://doi.org/10.1109/CAHPC.2018.8645904 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/MortattiYA18 AU - Mortatti, Matheus AU - Yviquel, Hervé AU - Araujo, Guido TI - Automatic Ray-Tracer Cloud Offloading in OPENMP. BT - 30th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2018, Lyon, France, September 24-27, 2018 SP - 428 EP - 435 PY - 2018// DO - 10.1109/CAHPC.2018.8645871 UR - https://doi.org/10.1109/CAHPC.2018.8645871 ER - TY - JOUR ID - DBLP:journals/taco/MendoncaGAPAP17 AU - Mendonca, Gleison Souza Diniz AU - Guimarães, Breno Campos Ferreira AU - Alves, Péricles AU - Pereira, Márcio Machado AU - Araujo, Guido AU - Pereira, Fernando Magno Quintão TI - DawnCC: Automatic Annotation for Data Parallelism and Offloading. JO - ACM Trans. Archit. Code Optim. VL - 14 IS - 2 SP - 13:1 EP - 13:25 PY - 2017// DO - 10.1145/3084540 UR - https://doi.org/10.1145/3084540 UR - https://www.wikidata.org/entity/Q114614084 ER - TY - CPAPER ID - DBLP:conf/europar/SalamancaAA17 AU - Salamanca, Juan AU - Amaral, José Nelson AU - Araujo, Guido TI - Performance Evaluation of Thread-Level Speculation in Off-the-Shelf Hardware Transactional Memories. BT - Euro-Par 2017: Parallel Processing - 23rd International Conference on Parallel and Distributed Computing, Santiago de Compostela, Spain, August 28 - September 1, 2017, Proceedings SP - 607 EP - 621 PY - 2017// DO - 10.1007/978-3-319-64203-1_44 UR - https://doi.org/10.1007/978-3-319-64203-1_44 ER - TY - CPAPER ID - DBLP:conf/icpp/YviquelA17 AU - Yviquel, Hervé AU - Araujo, Guido TI - The Cloud as an OpenMP Offloading Device. BT - 46th International Conference on Parallel Processing, ICPP 2017, Bristol, United Kingdom, August 14-17, 2017 SP - 352 EP - 361 PY - 2017// DO - 10.1109/ICPP.2017.44 UR - https://doi.org/10.1109/ICPP.2017.44 UR - https://doi.ieeecomputersociety.org/10.1109/ICPP.2017.44 ER - TY - CPAPER ID - DBLP:conf/ics/CarvalhoAB17 AU - Carvalho, Joao P. L. de AU - Araujo, Guido AU - Baldassin, Alexandro TI - Revisiting phased transactional memory. BT - Proceedings of the International Conference on Supercomputing, ICS 2017, Chicago, IL, USA, June 14-16, 2017 SP - 25:1 EP - 25:10 PY - 2017// DO - 10.1145/3079079.3079094 UR - https://doi.org/10.1145/3079079.3079094 ER - TY - CPAPER ID - DBLP:conf/iwomp/PereiraSA17 AU - Pereira, Márcio Machado AU - Sousa, Rafael C. F. AU - Araujo, Guido TI - Compiling and Optimizing OpenMP 4.X Programs to OpenCL and SPIR. BT - Scaling OpenMP for Exascale Performance and Portability - 13th International Workshop on OpenMP, IWOMP 2017, Stony Brook, NY, USA, September 20-22, 2017, Proceedings SP - 48 EP - 61 PY - 2017// DO - 10.1007/978-3-319-65578-9_4 UR - https://doi.org/10.1007/978-3-319-65578-9_4 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/SousaPPA17 AU - Sousa, Rafael Cardoso Fernandes AU - Pereira, Márcio Machado AU - Pereira, Fernando Magno Quintão AU - Araujo, Guido TI - Data Coherence Analysis and Optimization for Heterogeneous Computing. BT - 29th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2017, Campinas, Brazil, October 17-20, 2017 SP - 9 EP - 16 PY - 2017// DO - 10.1109/SBAC-PAD.2017.9 UR - https://doi.org/10.1109/SBAC-PAD.2017.9 UR - https://doi.ieeecomputersociety.org/10.1109/SBAC-PAD.2017.9 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/ZegarraPMA17 AU - Zegarra, Maicol AU - Pereira, Márcio Machado AU - Martorell, Xavier AU - Araujo, Guido TI - Automatic Scan Parallelization in OpenMP. BT - 2017 International Symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PAD Workshops, Campinas, Brazil, October 17-20, 2017 SP - 85 EP - 90 PY - 2017// DO - 10.1109/SBAC-PADW.2017.23 UR - https://doi.org/10.1109/SBAC-PADW.2017.23 UR - https://doi.ieeecomputersociety.org/10.1109/SBAC-PADW.2017.23 ER - TY - JOUR ID - DBLP:journals/pc/PereiraGAA16 AU - Pereira, Márcio Machado AU - Gaudet, Matthew AU - Amaral, José Nelson AU - Araujo, Guido TI - Study of hardware transactional memory characteristics and serialization policies on Haswell. JO - Parallel Comput. VL - 54 SP - 46 EP - 58 PY - 2016// DO - 10.1016/J.PARCO.2015.12.002 UR - https://doi.org/10.1016/j.parco.2015.12.002 ER - TY - CPAPER ID - DBLP:conf/dsd/SuritaCAA16 AU - Surita, Rodrigo C. AU - Côrtes, Mario Lúcio AU - Aranha, Diego F. AU - Araujo, Guido TI - Cylindrical Reconvergence Physical Unclonable Function. BT - 2016 Euromicro Conference on Digital System Design, DSD 2016, Limassol, Cyprus, August 31 - September 2, 2016 SP - 446 EP - 453 PY - 2016// DO - 10.1109/DSD.2016.100 UR - https://doi.org/10.1109/DSD.2016.100 UR - https://doi.ieeecomputersociety.org/10.1109/DSD.2016.100 ER - TY - CPAPER ID - DBLP:conf/hotchips/DallouLAMBFBS16 AU - Dallou, Tamer AU - Lucas, Divino Cesar Soares AU - Araujo, Guido AU - Morais, Lucas AU - Barbosa, Eduardo Ferreira AU - Frank, Michael AU - Bagley, Richard AU - Sayana, Raj TI - Task parallel programming model + hardware acceleration = performance advantage. BT - 2016 IEEE Hot Chips 28 Symposium (HCS), Cupertino, CA, USA, August 21-23, 2016 SP - 1 PY - 2016// DO - 10.1109/HOTCHIPS.2016.7936235 UR - https://doi.org/10.1109/HOTCHIPS.2016.7936235 ER - TY - CPAPER ID - DBLP:conf/ipps/SalamancaAA16 AU - Salamanca, Juan AU - Amaral, José Nelson AU - Araujo, Guido TI - Evaluating and Improving Thread-Level Speculation in Hardware Transactional Memories. BT - 2016 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2016, Chicago, IL, USA, May 23-27, 2016 SP - 586 EP - 595 PY - 2016// DO - 10.1109/IPDPS.2016.84 UR - https://doi.org/10.1109/IPDPS.2016.84 UR - https://doi.ieeecomputersociety.org/10.1109/IPDPS.2016.84 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/MendoncaGAPPA16 AU - Mendonca, Gleison Souza Diniz AU - Guimarães, Breno Campos Ferreira AU - Alves, Péricles Rafael Oliveira AU - Pereira, Fernando Magno Quintão AU - Pereira, Márcio Machado AU - Araujo, Guido TI - Automatic Insertion of Copy Annotation in Data-Parallel Programs. BT - 28th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2016, Los Angeles, CA, USA, October 26-28, 2016 SP - 34 EP - 41 PY - 2016// DO - 10.1109/SBAC-PAD.2016.13 UR - https://doi.org/10.1109/SBAC-PAD.2016.13 UR - https://doi.ieeecomputersociety.org/10.1109/SBAC-PAD.2016.13 ER - TY - CPAPER ID - DBLP:conf/spire/LouzaGZAT16 AU - Louza, Felipe A. AU - Gog, Simon AU - Zanotto, Leandro AU - Araujo, Guido AU - Telles, Guilherme P. TI - Parallel Computation for the All-Pairs Suffix-Prefix Problem. BT - String Processing and Information Retrieval - 23rd International Symposium, SPIRE 2016, Beppu, Japan, October 18-20, 2016, Proceedings SP - 122 EP - 132 PY - 2016// DO - 10.1007/978-3-319-46049-9_12 UR - https://doi.org/10.1007/978-3-319-46049-9_12 ER - TY - JOUR ID - DBLP:journals/ijpp/AraujoGPCAD15 AU - Araujo, Guido AU - Gaudiot, Jean-Luc AU - Parashar, Manish AU - Chiou, Derek AU - Amaral, José Nelson AU - Das, Chita R. TI - Guest Editorial: SBAC-PAD 2013. JO - Int. J. Parallel Program. VL - 43 IS - 6 SP - 961 EP - 964 PY - 2015// DO - 10.1007/S10766-015-0377-2 UR - https://doi.org/10.1007/s10766-015-0377-2 ER - TY - CPAPER ID - DBLP:conf/codes/HoffmanCAA15 AU - Hoffman, Caio AU - Côrtes, Mario Lúcio AU - Aranha, Diego F. AU - Araujo, Guido TI - Computer security by hardware-intrinsic authentication. BT - 2015 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015, Amsterdam, Netherlands, October 4-9, 2015 SP - 143 EP - 152 PY - 2015// DO - 10.1109/CODESISSS.2015.7331377 UR - https://doi.org/10.1109/CODESISSS.2015.7331377 UR - http://dl.acm.org/citation.cfm?id=2830856 ER - TY - CPAPER ID - DBLP:conf/ieeehpcs/LucasA15 AU - Lucas, Divino Cesar S. AU - Araujo, Guido TI - The Batched DOACROSS loop parallelization algorithm. BT - 2015 International Conference on High Performance Computing & Simulation, HPCS 2015, Amsterdam, Netherlands, July 20-24, 2015 SP - 476 EP - 483 PY - 2015// DO - 10.1109/HPCSIM.2015.7237079 UR - https://doi.org/10.1109/HPCSim.2015.7237079 ER - TY - CPAPER ID - DBLP:conf/ppopp/BaldassinBA15 AU - Baldassin, Alexandro AU - Borin, Edson AU - Araujo, Guido TI - Performance implications of dynamic memory allocators on transactional memory systems. BT - Proceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2015, San Francisco, CA, USA, February 7-11, 2015 SP - 87 EP - 96 PY - 2015// DO - 10.1145/2688500.2688504 UR - https://doi.org/10.1145/2688500.2688504 UR - https://doi.org/10.1145/2858788.2688504 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/SalamancaAA15 AU - Salamanca, Juan AU - Amaral, José Nelson AU - Araujo, Guido TI - Using Hardware Transactional Memory to Enable Speculative Trace Optimization. BT - 2015 International Symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PAD Workshops, Florianópolis, Brazil, October 18-21, 2015 SP - 1 EP - 6 PY - 2015// DO - 10.1109/SBAC-PADW.2015.13 UR - https://doi.org/10.1109/SBAC-PADW.2015.13 UR - https://doi.ieeecomputersociety.org/10.1109/SBAC-PADW.2015.13 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/GaudetAA15 AU - Gaudet, Matthew AU - Araujo, Guido AU - Amaral, José Nelson TI - Serialization Management for Best-Effort Hardware Transactional Memory. BT - 27th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2015, Florianópolis, Brazil, October 17-21, 2015 SP - 138 EP - 145 PY - 2015// DO - 10.1109/SBAC-PAD.2015.11 UR - https://doi.org/10.1109/SBAC-PAD.2015.11 UR - https://doi.ieeecomputersociety.org/10.1109/SBAC-PAD.2015.11 ER - TY - CPAPER ID - DBLP:conf/sbcci/CapovillaCA15 AU - Capovilla, Jefferson AU - Côrtes, Mario Lúcio AU - Araujo, Guido TI - Improving the Statistical Variability of Delay-based Physical Unclonable Functions. BT - Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, SBCCI 2015, Salvador, Brazil, August 31 - September 4, 2015 SP - 41:1 EP - 41:7 PY - 2015// DO - 10.1145/2800986.2801010 UR - https://doi.org/10.1145/2800986.2801010 ER - TY - JOUR ID - DBLP:journals/ijpp/BorinABW14 AU - Borin, Edson AU - Araujo, Guido AU - Breternitz, Maurício, Jr. AU - Wu, Youfeng TI - Microcode Compression Using Structured-Constrained Clustering. JO - Int. J. Parallel Program. VL - 42 IS - 1 SP - 140 EP - 164 PY - 2014// DO - 10.1007/S10766-012-0206-9 UR - https://doi.org/10.1007/s10766-012-0206-9 UR - https://www.wikidata.org/entity/Q58071479 ER - TY - CPAPER ID - DBLP:conf/date/HoffmanRAA14 AU - Hoffman, Caio AU - Ramos, Luiz AU - Azevedo, Rodolfo AU - Araujo, Guido TI - Wear-out analysis of Error Correction Techniques in Phase-Change Memory. BT - Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014 SP - 1 EP - 4 PY - 2014// DO - 10.7873/DATE.2014.047 UR - https://doi.org/10.7873/DATE.2014.047 UR - http://dl.acm.org/citation.cfm?id=2616647 ER - TY - CPAPER ID - DBLP:conf/icpp/PereiraAA14 AU - Pereira, Márcio Machado AU - Amaral, José Nelson AU - Araujo, Guido TI - Measuring Effective Work to Reward Success in Dynamic Transaction Scheduling. BT - 43rd International Conference on Parallel Processing, ICPP 2014, Minneapolis, MN, USA, September 9-12, 2014 SP - 141 EP - 150 PY - 2014// DO - 10.1109/ICPP.2014.23 UR - https://doi.org/10.1109/ICPP.2014.23 UR - https://doi.ieeecomputersociety.org/10.1109/ICPP.2014.23 ER - TY - CPAPER ID - DBLP:conf/iwomp/SalamancaMA14 AU - Salamanca, Juan AU - Mattos, Luis AU - Araujo, Guido TI - Loop-Carried Dependence Verification in OpenMP. BT - Using and Improving OpenMP for Devices, Tasks, and More - 10th International Workshop on OpenMP, IWOMP 2014, Salvador, Brazil, September 28-30, 2014. Proceedings SP - 87 EP - 102 PY - 2014// DO - 10.1007/978-3-319-11454-5_7 UR - https://doi.org/10.1007/978-3-319-11454-5_7 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/PereiraGAA14 AU - Pereira, Márcio Machado AU - Gaudet, Matthew AU - Amaral, José Nelson AU - Araujo, Guido TI - Multi-dimensional Evaluation of Haswell's Transactional Memory Performance. BT - 26th IEEE International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2014, Paris, France, October 22-24, 2014 SP - 144 EP - 151 PY - 2014// DO - 10.1109/SBAC-PAD.2014.33 UR - https://doi.org/10.1109/SBAC-PAD.2014.33 UR - https://doi.ieeecomputersociety.org/10.1109/SBAC-PAD.2014.33 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/WottrichAA14 AU - Wottrich, Rodolfo AU - Azevedo, Rodolfo AU - Araujo, Guido TI - Cloud-based OpenMP Parallelization Using a MapReduce Runtime. BT - 26th IEEE International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2014, Paris, France, October 22-24, 2014 SP - 334 EP - 341 PY - 2014// DO - 10.1109/SBAC-PAD.2014.46 UR - https://doi.org/10.1109/SBAC-PAD.2014.46 UR - https://doi.ieeecomputersociety.org/10.1109/SBAC-PAD.2014.46 ER - TY - JOUR ID - DBLP:journals/ijpp/NicacioBA13 AU - Nicácio, Daniel AU - Baldassin, Alexandro AU - Araujo, Guido TI - Transaction Scheduling Using Dynamic Conflict Avoidance. JO - Int. J. Parallel Program. VL - 41 IS - 1 SP - 89 EP - 110 PY - 2013// DO - 10.1007/S10766-012-0205-X UR - https://doi.org/10.1007/s10766-012-0205-x ER - TY - JOUR ID - DBLP:journals/spe/LoureiroPA13 AU - Loureiro, André AU - Porto, João Paulo AU - Araujo, Guido TI - Extending decoupled software pipeline to parallelize Java programs. JO - Softw. Pract. Exp. VL - 43 IS - 5 SP - 525 EP - 541 PY - 2013// DO - 10.1002/SPE.2120 UR - https://doi.org/10.1002/spe.2120 ER - TY - CPAPER ID - DBLP:conf/hipc/BaixoPA13 AU - Baixo, Andre AU - Porto, João Paulo AU - Araujo, Guido TI - Cache-based cross-iteration coherence for speculative parallelization. BT - 20th Annual International Conference on High Performance Computing, HiPC 2013, Bengaluru (Bangalore), Karnataka, India, December 18-21, 2013 SP - 216 EP - 225 PY - 2013// DO - 10.1109/HIPC.2013.6799113 UR - https://doi.org/10.1109/HiPC.2013.6799113 UR - https://doi.ieeecomputersociety.org/10.1109/HiPC.2013.6799113 ER - TY - CPAPER ID - DBLP:conf/hipc/PereiraBAB13 AU - Pereira, Márcio Machado AU - Baldassin, Alexandro AU - Araujo, Guido AU - Buzato, Luiz Eduardo TI - Transaction scheduling using conflict avoidance and Contention Intensity. BT - 20th Annual International Conference on High Performance Computing, HiPC 2013, Bengaluru (Bangalore), Karnataka, India, December 18-21, 2013 SP - 236 EP - 245 PY - 2013// DO - 10.1109/HIPC.2013.6799126 UR - https://doi.org/10.1109/HiPC.2013.6799126 UR - https://doi.ieeecomputersociety.org/10.1109/HiPC.2013.6799126 ER - TY - CPAPER ID - DBLP:conf/iiswc/CesarADRBA13 AU - Lucas, Divino Cesar S. AU - Auler, Rafael AU - Dalibera, Rafael AU - Rigo, Sandro AU - Borin, Edson AU - Araujo, Guido TI - Modeling virtual machines misprediction overhead. BT - Proceedings of the IEEE International Symposium on Workload Characterization, IISWC 2013, Portland, OR, USA, September 22-24, 2013 SP - 153 EP - 162 PY - 2013// DO - 10.1109/IISWC.2013.6704681 UR - https://doi.org/10.1109/IISWC.2013.6704681 UR - https://doi.ieeecomputersociety.org/10.1109/IISWC.2013.6704681 ER - TY - JOUR ID - DBLP:journals/dafes/AlbertiniRA12 AU - Albertini, Bruno C. AU - Rigo, Sandro AU - Araujo, Guido TI - Computational reflection and its application to platform verification. JO - Des. Autom. Embed. Syst. VL - 16 IS - 1 SP - 1 EP - 17 PY - 2012// DO - 10.1007/S10617-011-9082-6 UR - https://doi.org/10.1007/s10617-011-9082-6 ER - TY - JOUR ID - DBLP:journals/suscom/BergamaschiPRAA12 AU - Bergamaschi, Reinaldo A. AU - Piga, Leonardo AU - Rigo, Sandro AU - Azevedo, Rodolfo AU - Araújo, Guido TI - Data center power and performance optimization through global selection of P-states and utilization rates. JO - Sustain. Comput. Informatics Syst. VL - 2 IS - 4 SP - 198 EP - 208 PY - 2012// DO - 10.1016/J.SUSCOM.2012.10.001 UR - https://doi.org/10.1016/j.suscom.2012.10.001 ER - TY - CPAPER ID - DBLP:conf/wscad/LucasAB12 AU - Lucas, Divino Cesar S. AU - Araujo, Guido AU - Borin, Edson TI - Exploring Dynamic Program Behavior with Frames and Phases. BT - 13th Symposium on Computer Systems, WSCAD-SSC 2012, Petropolis, Brazil, October 17-19, 2012 SP - 118 EP - 125 PY - 2012// DO - 10.1109/WSCAD-SSC.2012.30 UR - https://doi.ieeecomputersociety.org/10.1109/WSCAD-SSC.2012.30 ER - TY - CPAPER ID - DBLP:conf/ica3pp/NicacioBA11 AU - Nicácio, Daniel AU - Baldassin, Alexandro AU - Araujo, Guido TI - LUTS: A Lightweight User-Level Transaction Scheduler. BT - Algorithms and Architectures for Parallel Processing - 11th International Conference, ICA3PP, Melbourne, Australia, October 24-26, 2011, Proceedings, Part I SP - 144 EP - 157 PY - 2011// DO - 10.1007/978-3-642-24650-0_13 UR - https://doi.org/10.1007/978-3-642-24650-0_13 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/BorinABW11 AU - Borin, Edson AU - Araujo, Guido AU - Breternitz, Maurício, Jr. AU - Wu, Youfeng TI - Structure-Constrained Microcode Compression. BT - 23rd International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2011, Vitória, Espírito Santo, Brazil, October 26-29, 2011 SP - 104 EP - 111 PY - 2011// DO - 10.1109/SBAC-PAD.2011.32 UR - https://doi.org/10.1109/SBAC-PAD.2011.32 UR - https://doi.ieeecomputersociety.org/10.1109/SBAC-PAD.2011.32 UR - https://www.wikidata.org/entity/Q58071516 ER - TY - CPAPER ID - DBLP:conf/acsac/GalloKDALA10 AU - Gallo, Roberto AU - Kawakami, Henrique AU - Dahab, Ricardo AU - Azevedo, Rafael AU - Lima, Saulo AU - Araujo, Guido TI - T-DRE: a hardware trusted computing base for direct recording electronic vote machines. BT - Twenty-Sixth Annual Computer Security Applications Conference, ACSAC 2010, Austin, Texas, USA, 6-10 December 2010 SP - 191 EP - 198 PY - 2010// DO - 10.1145/1920261.1920291 UR - https://doi.org/10.1145/1920261.1920291 ER - TY - CPAPER ID - DBLP:conf/ica3pp/NicacioA10 AU - Nicácio, Daniel AU - Araujo, Guido TI - Reducing False Aborts in STM Systems. BT - Algorithms and Architectures for Parallel Processing, 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings. Part I SP - 499 EP - 510 PY - 2010// DO - 10.1007/978-3-642-13119-6_43 UR - https://doi.org/10.1007/978-3-642-13119-6_43 ER - TY - CPAPER ID - DBLP:conf/isca/PortoABW10 AU - Porto, João Paulo AU - Araujo, Guido AU - Borin, Edson AU - Wu, Youfeng TI - Trace Execution Automata in Dynamic Binary Translation. BT - Computer Architecture - ISCA 2010 International Workshops A4MMC, AMAS-BT, EAMA, WEED, WIOSCA, Saint-Malo, France, June 19-23, 2010, Revised Selected Papers SP - 99 EP - 116 PY - 2010// DO - 10.1007/978-3-642-24322-6_10 UR - https://doi.org/10.1007/978-3-642-24322-6_10 ER - TY - CPAPER ID - DBLP:conf/isca/SouzaNA10 AU - Souza, Maxwell AU - Nicácio, Daniel AU - Araujo, Guido TI - ISAMAP: Instruction Mapping Driven by Dynamic Binary Translation. BT - Computer Architecture - ISCA 2010 International Workshops A4MMC, AMAS-BT, EAMA, WEED, WIOSCA, Saint-Malo, France, June 19-23, 2010, Revised Selected Papers SP - 117 EP - 138 PY - 2010// DO - 10.1007/978-3-642-24322-6_11 UR - https://doi.org/10.1007/978-3-642-24322-6_11 ER - TY - CONF ID - DBLP:conf/sbcci/2010 ED - Martino, João Antonio ED - Araujo, Guido ED - Orailoglu, Alex ED - Klein, Felipe TI - Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2010, São Paulo, Brazil, September 6-9, 2010 PY - 2010// PB - ACM SN - ISBN 978-1-4503-0152-7 ER - TY - JOUR ID - DBLP:journals/cal/BaldassinKAAC09 AU - Baldassin, Alexandro AU - Klein, Felipe AU - Araujo, Guido AU - Azevedo, Rodolfo AU - Centoducatte, Paulo TI - Characterizing the Energy Consumption of Software Transactional Memory. JO - IEEE Comput. Archit. Lett. VL - 8 IS - 2 SP - 56 EP - 59 PY - 2009// DO - 10.1109/L-CA.2009.47 UR - https://doi.org/10.1109/L-CA.2009.47 UR - http://doi.ieeecomputersociety.org/10.1109/L-CA.2009.47 ER - TY - JOUR ID - DBLP:journals/tvlsi/KleinLASA09 AU - Klein, Felipe AU - Leao, Roberto AU - Araujo, Guido AU - Santos, Luiz C. V. dos AU - Azevedo, Rodolfo TI - A Multi-Model Engine for High-Level Power Estimation Accuracy Optimization. JO - IEEE Trans. Very Large Scale Integr. Syst. VL - 17 IS - 5 SP - 660 EP - 673 PY - 2009// DO - 10.1109/TVLSI.2009.2013627 UR - https://doi.org/10.1109/TVLSI.2009.2013627 ER - TY - CPAPER ID - DBLP:conf/sbcci/KleinBACA09 AU - Klein, Felipe AU - Baldassin, Alexandro AU - Araujo, Guido AU - Centoducatte, Paulo AU - Azevedo, Rodolfo TI - On the energy-efficiency of software transactional memory. BT - Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009 PY - 2009// DO - 10.1145/1601896.1601938 UR - https://doi.org/10.1145/1601896.1601938 ER - TY - JOUR ID - DBLP:journals/jucs/SantosAA08 AU - Santos, Ricardo AU - Azevedo, Rodolfo AU - Araujo, Guido TI - Instruction Scheduling Based on Subgraph Isomorphism for a High Performance Computer Processor. JO - J. Univers. Comput. Sci. VL - 14 IS - 21 SP - 3465 EP - 3480 PY - 2008// DO - 10.3217/JUCS-014-21-3465 UR - https://doi.org/10.3217/jucs-014-21-3465 ER - TY - JOUR ID - DBLP:journals/vlsisp/JuliatoALD07 AU - Juliato, Marcio AU - Araujo, Guido AU - López, Julio AU - Dahab, Ricardo TI - A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over F_2¹⁶³ using Gaussian Normal Bases. JO - J. VLSI Signal Process. VL - 47 IS - 1 SP - 59 EP - 76 PY - 2007// DO - 10.1007/S11265-006-0015-8 UR - https://doi.org/10.1007/s11265-006-0015-8 ER - TY - CPAPER ID - DBLP:conf/codes/AlbertiniRAABA07 AU - Albertini, Bruno C. AU - Rigo, Sandro AU - Araujo, Guido AU - Araújo, Cristiano C. de AU - Barros, Edna AU - Azevedo, Willians TI - A computational reflection mechanism to support platform debugging in SystemC. BT - Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007 SP - 81 EP - 86 PY - 2007// DO - 10.1145/1289816.1289838 UR - https://doi.org/10.1145/1289816.1289838 ER - TY - CPAPER ID - DBLP:conf/fpt/CappabiancoAF07 AU - Cappabianco, Fabio Augusto AU - Araujo, Guido AU - Falcão, Alexandre X. TI - The Image Forest Transform Architecture. BT - 2007 International Conference on Field-Programmable Technology, ICFPT 2007, Kitakyushu, Japan, December 12-14, 2007 SP - 137 EP - 144 PY - 2007// DO - 10.1109/FPT.2007.4439242 UR - https://doi.org/10.1109/FPT.2007.4439242 ER - TY - CPAPER ID - DBLP:conf/islped/KleinAALS07 AU - Klein, Felipe AU - Araujo, Guido AU - Azevedo, Rodolfo AU - Leao, Roberto AU - Santos, Luiz C. V. dos TI - A multi-model power estimation engine for accuracy optimization. BT - Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007 SP - 280 EP - 285 PY - 2007// DO - 10.1145/1283780.1283840 UR - https://doi.org/10.1145/1283780.1283840 ER - TY - CPAPER ID - DBLP:conf/isvlsi/MacielARAA07 AU - Maciel, Richard AU - Albertini, Bruno C. AU - Rigo, Sandro AU - Araujo, Guido AU - Azevedo, Rodolfo TI - A Methodology and Toolset to Enable SystemC and VHDL Co-simulation. BT - 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil SP - 351 EP - 356 PY - 2007// DO - 10.1109/ISVLSI.2007.9 UR - https://doi.org/10.1109/ISVLSI.2007.9 UR - https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.9 ER - TY - CPAPER ID - DBLP:conf/isvlsi/KleinAALS07 AU - Klein, Felipe AU - Araujo, Guido AU - Azevedo, Rodolfo AU - Leao, Roberto AU - Santos, Luiz C. V. dos TI - On the Limitations of Power Macromodeling Techniques. BT - 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil SP - 395 EP - 400 PY - 2007// DO - 10.1109/ISVLSI.2007.74 UR - https://doi.org/10.1109/ISVLSI.2007.74 UR - https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.74 ER - TY - CPAPER ID - DBLP:conf/rsp/KronbauerBACRAA07 AU - Kronbauer, Fernando AU - Baldassin, Alexandro AU - Albertini, Bruno C. AU - Centoducatte, Paulo AU - Rigo, Sandro AU - Araujo, Guido AU - Azevedo, Rodolfo TI - A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation. BT - 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 28-30 May 2007, Porto Alegre, RS, Brazil SP - 123 EP - 129 PY - 2007// DO - 10.1109/RSP.2007.6 UR - https://doi.org/10.1109/RSP.2007.6 UR - https://doi.ieeecomputersociety.org/10.1109/RSP.2007.6 ER - TY - JOUR ID - DBLP:journals/tecs/OttoniOAL06 AU - Ottoni, Desiree AU - Ottoni, Guilherme AU - Araujo, Guido AU - Leupers, Rainer TI - Offset assignment using simultaneous variable coalescing. JO - ACM Trans. Embed. Comput. Syst. VL - 5 IS - 4 SP - 864 EP - 883 PY - 2006// DO - 10.1145/1196636.1196641 UR - https://doi.org/10.1145/1196636.1196641 ER - TY - CPAPER ID - DBLP:conf/asap/SantosAA06 AU - Santos, Ricardo AU - Azevedo, Rodolfo AU - Araujo, Guido TI - 2D-VLIW: An Architecture Based on the Geometry of Computation. BT - 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA SP - 87 EP - 94 PY - 2006// DO - 10.1109/ASAP.2006.1 UR - https://doi.org/10.1109/ASAP.2006.1 UR - https://doi.ieeecomputersociety.org/10.1109/ASAP.2006.1 ER - TY - CPAPER ID - DBLP:conf/cgo/BorinWWA06 AU - Borin, Edson AU - Wang, Cheng AU - Wu, Youfeng AU - Araujo, Guido TI - Software-Based Transparent and Comprehensive Control-Flow Error Detection. BT - Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 26-29 March 2006, New York, New York, USA SP - 333 EP - 345 PY - 2006// DO - 10.1109/CGO.2006.33 UR - https://doi.org/10.1109/CGO.2006.33 UR - https://doi.ieeecomputersociety.org/10.1109/CGO.2006.33 UR - http://dl.acm.org/citation.cfm?id=1122415 ER - TY - CPAPER ID - DBLP:conf/iccd/BorinBWA06 AU - Borin, Edson AU - Breternitz, Maurício, Jr. AU - Wu, Youfeng AU - Araujo, Guido TI - Clustering-Based Microcode Compression. BT - 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA SP - 189 EP - 196 PY - 2006// DO - 10.1109/ICCD.2006.4380816 UR - https://doi.org/10.1109/ICCD.2006.4380816 UR - https://doi.ieeecomputersociety.org/10.1109/ICCD.2006.4380816 ER - TY - CPAPER ID - DBLP:conf/ipps/SantosAA06 AU - Santos, Ricardo AU - Azevedo, Rodolfo AU - Araujo, Guido TI - Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach. BT - 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece PY - 2006// DO - 10.1109/IPDPS.2006.1639485 UR - https://doi.org/10.1109/IPDPS.2006.1639485 UR - https://doi.ieeecomputersociety.org/10.1109/IPDPS.2006.1639485 ER - TY - JOUR ID - DBLP:journals/dafes/AraujoBMASPL05 AU - Araujo, Guido AU - Barros, Edna AU - Melcher, Elmar U. K. AU - Azevedo, Rodolfo AU - Silva, Karina R. G. da AU - Prado, Bruno O. AU - Lima, Manoel Eusébio de TI - A SystemC-only design methodology and the CINE-IP multimedia platform. JO - Des. Autom. Embed. Syst. VL - 10 IS - 2-3 SP - 181 EP - 202 PY - 2005// DO - 10.1007/S10617-006-9585-8 UR - https://doi.org/10.1007/s10617-006-9585-8 ER - TY - JOUR ID - DBLP:journals/dafes/AraujoGBRAA05 AU - Araújo, Cristiano C. de AU - Gomes, Millena AU - Barros, Edna AU - Rigo, Sandro AU - Azevedo, Rodolfo AU - Araujo, Guido TI - Platform designer: An approach for modeling multiprocessor platforms based on SystemC. JO - Des. Autom. Embed. Syst. VL - 10 IS - 4 SP - 253 EP - 283 PY - 2005// DO - 10.1007/S10617-006-0654-9 UR - https://doi.org/10.1007/s10617-006-0654-9 ER - TY - JOUR ID - DBLP:journals/ijpp/AzevedoRBAAB05 AU - Azevedo, Rodolfo AU - Rigo, Sandro AU - Bartholomeu, Marcus AU - Araujo, Guido AU - Araújo, Cristiano C. de AU - Barros, Edna TI - The ArchC Architecture Description Language and Tools. JO - Int. J. Parallel Program. VL - 33 IS - 5 SP - 453 EP - 484 PY - 2005// DO - 10.1007/S10766-005-7301-0 UR - https://doi.org/10.1007/s10766-005-7301-0 ER - TY - JOUR ID - DBLP:journals/jea/SouzaLAM05 AU - Souza, Cid C. de AU - Lima, André M. AU - Araujo, Guido AU - Moreano, Nahri TI - The datapath merging problem in reconfigurable systems: Complexity, dual bounds and heuristic evaluation. JO - ACM J. Exp. Algorithmics VL - 10 PY - 2005// DO - 10.1145/1064546.1180613 UR - https://doi.org/10.1145/1064546.1180613 ER - TY - JOUR ID - DBLP:journals/sigarch/BorinWWA05 AU - Borin, Edson AU - Wang, Cheng AU - Wu, Youfeng AU - Araujo, Guido TI - Dynamic binary control-flow errors detection. JO - SIGARCH Comput. Archit. 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BT - Forum on specification and Design Languages, FDL 2005, September 27-30, 2005, Lausanne, Switzerland, Proceedings SP - 303 EP - 315 PY - 2005// UR - http://www.ecsi-association.org/ecsi/main.asp?l1=library&fn=def&id=480 ER - TY - CPAPER ID - DBLP:conf/fpt/JuliatoALD05 AU - Juliato, Marcio AU - Araujo, Guido AU - López-Hernández, Julio César AU - Dahab, Ricardo TI - A custom instruction approach for hardware and software implementations of finite field arithmetic over F_2⁶³ using Gaussian normal bases. BT - Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, FPT 2005, 11-14 December 2005, Singapore SP - 5 EP - 12 PY - 2005// ER - TY - CPAPER ID - DBLP:conf/issoc/KleinAA05 AU - Klein, Felipe AU - Azevedo, Rodolfo AU - Araujo, Guido TI - High-Level Switching Activity Prediction Through Sampled Monitored Simulation. BT - Proceedings of the 2005 International Symposium on System-on-Chip, Tampere, Finland, November 15-17, 2005 SP - 161 EP - 166 PY - 2005// DO - 10.1109/ISSOC.2005.1595668 UR - https://doi.org/10.1109/ISSOC.2005.1595668 ER - TY - CPAPER ID - DBLP:conf/sbcci/BilloAACN05 AU - Billo, Eduardo Afonso AU - Azevedo, Rodolfo AU - Araujo, Guido AU - Centoducatte, Paulo AU - Netto, Eduardo Braulio Wanderley TI - Design of a decompressor engine on a SPARC processor. BT - Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005 SP - 110 EP - 114 PY - 2005// DO - 10.1145/1081081.1081113 UR - https://doi.org/10.1145/1081081.1081113 ER - TY - JOUR ID - DBLP:journals/tecs/HuangMMA04 AU - Huang, Zhining AU - Malik, Sharad AU - Moreano, Nahri AU - Araujo, Guido TI - The design of dynamically reconfigurable datapath coprocessors. JO - ACM Trans. Embed. Comput. Syst. VL - 3 IS - 2 SP - 361 EP - 384 PY - 2004// DO - 10.1145/993396.993403 UR - https://doi.org/10.1145/993396.993403 ER - TY - CPAPER ID - DBLP:conf/dac/NettoACA04 AU - Netto, Eduardo Braulio Wanderley AU - Azevedo, Rodolfo AU - Centoducatte, Paulo AU - Araujo, Guido TI - Multi-profile based code compression. BT - Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004 SP - 244 EP - 249 PY - 2004// DO - 10.1145/996566.996635 UR - https://doi.org/10.1145/996566.996635 ER - TY - CPAPER ID - DBLP:conf/date/VianaBRAA04 AU - Viana, Pablo AU - Barros, Edna AU - Rigo, Sandro AU - Azevedo, Rodolfo AU - Araujo, Guido TI - Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology. BT - 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France SP - 734 EP - 735 PY - 2004// DO - 10.1109/DATE.2004.1268953 UR - https://doi.org/10.1109/DATE.2004.1268953 UR - https://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268953 UR - http://dl.acm.org/citation.cfm?id=969012 ER - TY - CPAPER ID - DBLP:conf/estimedia/BorinKMAA04 AU - Borin, Edson AU - Klein, Felipe AU - Moreano, Nahri AU - Azevedo, Rodolfo AU - Araujo, Guido TI - Fast instruction set custornization. BT - Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2004, Stockholm, Sweden, September 6-7, 2004 SP - 53 EP - 58 PY - 2004// DO - 10.1109/ESTMED.2004.1359704 UR - https://doi.org/10.1109/ESTMED.2004.1359704 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/NettoACA04 AU - Netto, Eduardo Braulio Wanderley AU - Azevedo, Rodolfo AU - Centoducatte, Paulo AU - Araujo, Guido TI - Multi-Profile Instruction Based Compression. BT - 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 27-29 October 2004, Foz do Iguacu, Brazil SP - 23 EP - 29 PY - 2004// DO - 10.1109/SBAC-PAD.2004.26 UR - https://doi.org/10.1109/SBAC-PAD.2004.26 UR - https://doi.ieeecomputersociety.org/10.1109/CAHPC.2004.26 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/RigoABA04 AU - Rigo, Sandro AU - Araujo, Guido AU - Bartholomeu, Marcus AU - Azevedo, Rodolfo TI - ArchC: A SystemC-Based Architecture Description Language. BT - 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 27-29 October 2004, Foz do Iguacu, Brazil SP - 66 EP - 73 PY - 2004// DO - 10.1109/SBAC-PAD.2004.8 UR - https://doi.org/10.1109/SBAC-PAD.2004.8 UR - https://doi.ieeecomputersociety.org/10.1109/CAHPC.2004.8 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/BartholomeuARA04 AU - Bartholomeu, Marcus AU - Azevedo, Rodolfo AU - Rigo, Sandro AU - Araujo, Guido TI - Optimizations for Compiled Simulation Using Instruction Type Information. BT - 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 27-29 October 2004, Foz do Iguacu, Brazil SP - 74 EP - 81 PY - 2004// DO - 10.1109/SBAC-PAD.2004.28 UR - https://doi.org/10.1109/SBAC-PAD.2004.28 UR - https://doi.ieeecomputersociety.org/10.1109/CAHPC.2004.28 ER - TY - CPAPER ID - DBLP:conf/sbcci/SilvaMAP04 AU - Silva, Karina R. G. da AU - Melcher, Elmar U. K. AU - Araujo, Guido AU - Pimenta, Valdiney Alves TI - An automatic testbench generation tool for a SystemC functional verification methodology. BT - Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004 SP - 66 EP - 70 PY - 2004// DO - 10.1145/1016568.1016592 UR - https://doi.org/10.1145/1016568.1016592 ER - TY - CPAPER ID - DBLP:conf/wcae/RigoJAAC04 AU - Rigo, Sandro AU - Juliato, Marcio AU - Azevedo, Rodolfo AU - Araujo, Guido AU - Centoducatte, Paulo TI - Teaching computer architecture using an architecture description language. BT - Proceedings of the 2004 workshop on Computer architecture education - Held in conjunction with the 31st International Symposium on Computer Architecture, WCAE@ISCA 2004, Munich, Germany, June 19, 2004 SP - 6 PY - 2004// DO - 10.1145/1275571.1275580 UR - https://doi.org/10.1145/1275571.1275580 ER - TY - CPAPER ID - DBLP:conf/wea/SouzaLMA04 AU - Souza, Cid C. de AU - Lima, André M. AU - Moreano, Nahri AU - Araujo, Guido TI - The Datapath Merging Problem in Reconfigurable Systems: Lower Bounds and Heuristic Evaluation. BT - Experimental and Efficient Algorithms, Third International Workshop, WEA 2004, Angra dos Reis, Brazil, May 25-28, 2004, Proceedings SP - 545 EP - 558 PY - 2004// DO - 10.1007/978-3-540-24838-5_40 UR - https://doi.org/10.1007/978-3-540-24838-5_40 ER - TY - JOUR ID - DBLP:journals/mj/OttoniA03 AU - Ottoni, Guilherme AU - Araujo, Guido TI - Address register allocation for arrays in loops of embedded programs. JO - Microelectron. J. VL - 34 IS - 11 SP - 1009 EP - 1018 PY - 2003// DO - 10.1016/S0026-2692(03)00169-1 UR - https://doi.org/10.1016/S0026-2692(03)00169-1 ER - TY - CPAPER ID - DBLP:conf/issoc/NettoACA03 AU - Netto, Eduardo Braulio Wanderley AU - Azevedo, Rodolfo AU - Centoducatte, Paulo AU - Araujo, Guido TI - Mixed static/dynamic profiling for dictionary based code compression. BT - Proceedings of the 2003 International Symposium on System-on-Chip, Tampere, Finland, November 19-21, 2003 SP - 159 EP - 163 PY - 2003// DO - 10.1109/ISSOC.2003.1267745 UR - https://doi.org/10.1109/ISSOC.2003.1267745 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/VianaBRAA03 AU - Viana, Pablo AU - Barros, Edna AU - Rigo, Sandro AU - Azevedo, Rodolfo AU - Araujo, Guido TI - Exploring Memory Hierarchy with ArchC. BT - 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2003), 10-12 November 2003, Sao Paulo, Brazil SP - 2 EP - 9 PY - 2003// DO - 10.1109/CAHPC.2003.1250315 UR - https://doi.org/10.1109/CAHPC.2003.1250315 UR - https://doi.ieeecomputersociety.org/10.1109/CAHPC.2003.1250315 ER - TY - CPAPER ID - DBLP:conf/scopes/OttoniOAL03 AU - Ottoni, Desiree AU - Ottoni, Guilherme AU - Araujo, Guido AU - Leupers, Rainer TI - Improving Offset Assignment through Simultaneous Variable Coalescing. BT - Software and Compilers for Embedded Systems, 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings SP - 285 EP - 297 PY - 2003// DO - 10.1007/978-3-540-39920-9_20 UR - https://doi.org/10.1007/978-3-540-39920-9_20 ER - TY - JOUR ID - DBLP:journals/todaes/AraujoOC02 AU - Araujo, Guido AU - Ottoni, Guilherme AU - Cintra, Marcelo Silva TI - Global array reference allocation. JO - ACM Trans. Design Autom. Electr. Syst. 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BT - Compiler Construction, 10th International Conference, CC 2001 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2001 Genova, Italy, April 2-6, 2001, Proceedings SP - 274 EP - 288 PY - 2001// DO - 10.1007/3-540-45306-7_19 UR - https://doi.org/10.1007/3-540-45306-7_19 ER - TY - JOUR ID - DBLP:journals/tvlsi/AraujoCAP00 AU - Araujo, Guido AU - Centoducatte, Paulo AU - Azevedo, Rodolfo AU - Pannain, Ricardo TI - Expression-tree-based algorithms for code compression on embedded RISC architectures. JO - IEEE Trans. Very Large Scale Integr. Syst. VL - 8 IS - 5 SP - 530 EP - 533 PY - 2000// DO - 10.1109/92.894158 UR - https://doi.org/10.1109/92.894158 ER - TY - CPAPER ID - DBLP:conf/lctrts/CintraA00 AU - Cintra, Marcelo Silva AU - Araujo, Guido TI - Array Reference Allocation Using SSA-Form and Live Range Growth. BT - Languages, Compilers, and Tools for Embedded Systems, ACM SIGPLAN Workshop LCTES 2000, Vancouver, BC, Canada, June 18, 2000, Proceedings SP - 48 EP - 62 PY - 2000// DO - 10.1007/3-540-45245-1_4 UR - https://doi.org/10.1007/3-540-45245-1_4 ER - TY - CPAPER ID - DBLP:conf/isss/CentoducattePA99 AU - Centoducatte, Paulo AU - Pannain, Ricardo AU - Araujo, Guido TI - Compressed Code Execution on DSP Architectures. BT - Proceedings of the 12th International Symposium on System Synthesis, ISSS '99, Boca Raton, Florida, USA, November 1-4, 1999. SP - 56 EP - 63 PY - 1999// DO - 10.1109/ISSS.1999.814261 UR - https://doi.org/10.1109/ISSS.1999.814261 UR - https://doi.ieeecomputersociety.org/10.1109/ISSS.1999.814261 UR - http://dl.acm.org/citation.cfm?id=857959 ER - TY - JOUR ID - DBLP:journals/todaes/AraujoM98 AU - Araujo, Guido AU - Malik, Sharad TI - Code generation for fixed-point DSPs. JO - ACM Trans. Design Autom. Electr. Syst. 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