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ORCIDCristiano Lazzari
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2010 – 2019
- 2013
[j6]Levent Aksoy
, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro:
Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 498-511 (2013)- [c23]Alexandre M. Amory, Matheus T. Moreira, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Cristiano Lazzari, Marcelo Soares Lubaszewski:
Evaluating the scalability of test buses. ISSoC 2013: 1-6 - 2012
- [j5]Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro:
High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications. Integr. 45(3): 294-306 (2012) - 2011
- [j4]Cristiano Lazzari, Jorge R. Fernandes, Paulo F. Flores, José Monteiro:
Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays. J. Low Power Electron. 7(2): 294-301 (2011) - [j3]Alexandre M. Amory, Cristiano Lazzari, Marcelo Lubaszewski, Fernando Gehm Moraes:
A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms. J. Parallel Distributed Comput. 71(5): 675-686 (2011) - [c22]Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro:
Efficient shift-adds design of digit-serial multiple constant multiplications. ACM Great Lakes Symposium on VLSI 2011: 61-66 - [c21]Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro:
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level. ISCAS 2011: 2737-2740 - [c20]Alexandre M. Amory, Cristiano Lazzari, Marcelo Lubaszewski, Fernando Gehm Moraes:
Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs. SBCCI 2011: 73-78 - 2010
- [c19]Cristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro:
A new quaternary FPGA based on a voltage-mode multi-valued circuit. DATE 2010: 1797-1802 - [c18]Marcus Ritt, Carlos Arthur Lang Lisbôa, Luigi Carro, Cristiano Lazzari:
A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAs. FPL 2010: 332-335 - [c17]Sidinei Ghissoni, Eduardo Costa, Cristiano Lazzari, José Monteiro, Levent Aksoy, Ricardo Reis:
Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. ICECS 2010: 859-862 - [c16]Cristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro:
Voltage-mode quaternary FPGAs: An evaluation of interconnections. ISCAS 2010: 869-872 - [c15]Cristiano Lazzari, Jorge R. Fernandes, Paulo F. Flores, José Monteiro:
An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs. PATMOS 2010: 84-93
2000 – 2009
- 2009
- [j2]Ricardo C. Goncalves da Silva, Cristiano Lazzari, Henri Boudinov, Luigi Carro:
CMOS voltage-mode quaternary look-up tables for multi-valued FPGAs. Microelectron. J. 40(10): 1466-1470 (2009) - [c14]Cristiano Lazzari, Adriel Ziesemer, Ricardo Reis:
An automated design methodology for layout generation targeting power leakage minimization. ICECS 2009: 81-84 - 2007
- [j1]Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel:
A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis. J. Electron. Test. 23(6): 625-633 (2007) - [c13]Adriel Ziesemer, Cristiano Lazzari, Ricardo Reis:
An Educational Tool for Design Automation of CMOS Cells. MSE 2007: 149-150 - [c12]Adriel Ziesemer, Cristiano Lazzari:
Transistor level automatic layout generator for non-complementary CMOS cells. VLSI-SoC 2007: 116-121 - [c11]Cristiano Lazzari, Cristiano Santos, Adriel Ziesemer, Lorena Anghel, Ricardo Reis:
Efficient timing closure with a transistor level design flow. VLSI-SoC 2007: 312-315 - 2006
- [c10]Cristiano Lazzari, Cristiano Santos, Ricardo Reis:
A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits. ICECS 2006: 660-663 - [c9]Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel:
Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study. IOLTS 2006: 165-172 - [c8]Lorena Anghel, Cristiano Lazzari, Michael Nicolaidis:
Multiple Defect Tolerant Devices for Unreliable Future Nanotechnologies. LATW 2006: 186-191 - 2005
- [c7]Cristiano Lazzari, Lorena Anghel, Ricardo A. L. Reis:
On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study. IOLTS 2005: 29-34 - [c6]Cristiano Lazzari, Lorena Anghel, Ricardo Reis:
A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming. VLSI-SoC 2005: 331-344 - 2004
- [c5]Cristiano Lazzari:
Automatic Full-Custom Layout Generation of Static CMOS Circuits Targeting Delay and Power Reduction. IFIP Student Forum 2004: 177-186 - [c4]Fabricio B. Bastian, Cristiano Lazzari, José Luís Almada Güntzel, Ricardo Reis:
A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool. PATMOS 2004: 732-741 - 2003
- [c3]Cristiano Santos, Gustavo Wilke, Cristiano Lazzari, Ricardo Reis, José Luís Almada Güntzel:
A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. SBCCI 2003: 303- - [c2]Cristiano Lazzari, Cristiano Viana Domingues, José Luís Almada Güntzel, Ricardo Augusto da Luz Reis:
A New Macro-cell Generation Strategy for three metal layer CMOS Technologies. VLSI-SOC 2003: 193-197 - [c1]Cristiano Lazzari, Cristiano Viana Domingues, José Luís Güntzel, Ricardo Reis:
A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits. VLSI-SoC (Selected Papers) 2003: 197-211
Coauthor Index
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