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ORCIDLuis Hernández 0003
Person information
- affiliation: Carlos III University, Electronic Technology Department, Madrid, Spain
Other persons with the same name
- Luis Hernández — disambiguation page
- Luis Hernández 0001
![[0000-0001-9011-0542]](https://dblp.org/img/orcid-mark.12x12.png "0000-0001-9011-0542")
— Polytechnic University of Valencia, Spain - Luis Hernández 0002 (aka: Luis Hernández-Callejo) — University of Valladolid, Department of Agricultural and Forestry Engineering, Spain
- Luis Antonio Hernández Ibáñez (aka: Luis Hernández 0004) — University of Coruña, A Coruña, Spain
- Luis Hernández-Martínez (aka: Luis Hernández 0005) — Instituto Nacional de Astrofisica Optica y Electronica, Puebla, Mexico
Other persons with a similar name
- Juan Luis Hernández Arellano (aka: Juan Luis Hernández, Juan Hernández 0002) — Universidad Autonoma de Ciudad Juárez, Mexico
- Luis Hernández Encinas — Consejo Superior de Investigaciones Cientificas, Madrid, Spain
- Luis A. Hernández Gómez (aka: Luis Alfonso Hernández Gómez)
- Luis Ángel Reyes Hernández
- José Luis Hernández-Hernández
- José Luis Hernández-Stefanoni
- Luis Hernandez
- Luis Hernandez-Garcia
- Luis A. Morales-Hernández (aka: Luis Alberto Morales-Hernández) — Universidad Autonoma de Queretaro, Mexico
- José Luis Hernández Ramos — Universidad de Murcia, Spain
- show all similar names
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2020 – today
- 2024
[j18]Victor Medina, Leidy Mabel Alvero-Gonzalez, Eric Gutierrez, Luis Hernández, Susana Patón:
Analysis of VCO-Based Continuous-Time ΣΔ ADCs Using a Subset of Phases as the Feedback Signal. IEEE Trans. Circuits Syst. II Express Briefs 71(6): 2946-2950 (2024)- [c56]Dante Loi, Javier Granizo, Luis Hernández:
A Scalable and PVT Invariant Spiking Neuron Using Asynchronous CMOS Logic. ISCAS 2024: 1-5 - [i2]Victor Medina, Rubén Garvi, Javier Granizo, Pedro Amaral, Luis Hernández:
A Second-Order Audio VCO-ADC with 103-dB-A Dynamic Range and Binary-Weighted Internal Architecture. CoRR abs/2405.07887 (2024) - 2023
- [j17]Victor Medina, Rubén Garvi, Eric Gutierrez, Susana Patón, Luis Hernández:
A Gray-Encoded Ring Oscillator for Efficient Frequency-to-Digital Conversion in VCO-Based ADCs. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 870-874 (2023) - [j16]Rubén Garvi, Javier Granizo, Eric Gutierrez, Victor Medina, Andreas Wiesbauer, Luis Hernández:
A VCO-ADC Linearized by a Capacitive Frequency-to-Current Converter. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 1841-1845 (2023) - [j15]Victor Medina, Rubén Garvi, Eric Gutierrez, Luis Hernández:
A VCO-Based ADC With Inherent Mixing Capability and Local Oscillator Suppression in 55-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3338-3342 (2023) - [c55]Diego Garcia, Javier Granizo, Luis Hernández:
Validation of a CMOS SNN network based on a time-domain threshold neuron circuit achieving 114.90 pJ/inference on MNIST. AICAS 2023: 1-5 - [c54]Javier Granizo, Rubén Garvi, Diego Garcia, Luis Hernández:
A CMOS LIF neuron based on a charge-powered oscillator with time-domain threshold logic. ISCAS 2023: 1-5 - [c53]Victor Medina, Dante Loi, Pieter Rombouts, Luis Hernández:
Analysis of in-band Spurious Tones of VCO-based Analog Filters and Mitigation Techniques. ISCAS 2023: 1-5 - [i1]Victor Medina, Pieter Rombouts, Luis Hernández:
A Different View of Sigma-Delta Modulators Under the Lens of Pulse Frequency Modulation. CoRR abs/2311.06983 (2023) - 2022
- [c52]Rubén Garvi, Javier Granizo, Angel Salvador, Luis Hernández:
A 55nm CMOS Linearized Oscillator for Audio VCO-ADCs achieving 78dBA of SNDR with $153\mu \mathrm{W}$. ICECS 2022 2022: 1-4 - [c51]Victor Medina, Rubén Garvi, Eric Gutierrez, Luis Hernández:
A maximally-digital VCO-ADC with inherent mixing input capability. ISCAS 2022: 1-5 - [c50]Pablo Vera, Dietmar Straeussnigg, Victor Medina, Luis Hernández, Susana Patón:
Optimal reconfiguration instant in ΣΔ Modulators. ISCAS 2022: 1225-1229 - [c49]Rubén Garvi, Eric Gutierrez, Victor Medina, Luis Hernández:
A Phase-Encoded Voice Features Extraction Circuit Using Digital Mixers and Analog Filters based on Ring Oscillators. ISCAS 2022: 1420-1424 - 2021
- [j14]Carlos Perez, Andrés Quintero, Pedro Amaral, Andreas Wiesbauer, Luis Hernández:
A 73dB-A Audio VCO-ADC Based on a Maximum Length Sequence Generator in 130nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(10): 3194-3198 (2021) - 2020
- [c48]Fernando Cardes, Victor Medina, Susana Patón, Luis Hernández:
Clock Jitter Analysis of Continuous-Time ΣΔ Modulators Based on a Relative Time-Base Projection. ISCAS 2020: 1 - [c47]Rubén Garvi, Leidy Mabel Alvero-Gonzalez, Carlos Perez, Eric Gutierrez, Luis Hernández:
VCO-ADC Linearization by Switched Capacitor Frequency-to-Current Conversion. ISCAS 2020: 1-5 - [c46]Victor Medina, Susana Patón, Eric Gutierrez, Luis Hernández:
A Model of Continuous-Time Sigma Delta Modulation Based on Pulse Frequency Encoding. ISCAS 2020: 1-5 - [c45]Eric Gutierrez, Carlos Perez, Susana Patón, Luis Hernández:
Low Power Phase-Encoded MAC Accelerator for Smart Sensors with VCO-based ADCs. MWSCAS 2020: 261-264
2010 – 2019
- 2019
- [j13]Andrés Quintero, Fernando Cardes, Carlos Perez, Cesare Buffa, Andreas Wiesbauer, Luis Hernández:
A VCO-Based CMOS Readout Circuit for Capacitive MEMS Microphones. Sensors 19(19): 4126 (2019) - [j12]Eric Gutierrez, Carlos Perez, Luis Hernández, Fernando Cardes, Violeta Petrescu, Sergio Walter, Ulrich Gaier:
A Pulse Frequency Modulation VCO-ADC in 40 nm. IEEE Trans. Circuits Syst. II Express Briefs 66-II(1): 51-55 (2019) - [j11]Fernando Cardes, Victor Medina, Susana Patón, Luis Hernández:
Clock Jitter Analysis of Continuous-Time ΣΔ Modulators Based on a Relative Time-Base Projection. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 920-929 (2019) - [c44]Leidy Mabel Alvero-Gonzalez, Luis Hernández, Eric Gutierrez:
Resolution Enhancement of VCO-based ADCs by Passive Interpolation and Phase Injection. DCIS 2019: 1-5 - [c43]Victor Medina, Leidy Mabel Alvero-Gonzalez, Eric Gutierrez, Susana Patón, Luis Hernández:
Continuous Time Sigma-Delta Modulator with VCO-based integrators and optimized NTF zeros. ICECS 2019: 470-473 - [c42]Eric Gutierrez, Leidy Mabel Alvero-Gonzalez, Luis Hernández, Pieter Rombouts:
VCO-ADCs with a Quadrature Band-Pass Noise-Transfer-Function. ISCAS 2019: 1-5 - [c41]Eric Gutierrez, Carlos Perez, Fernando Hernandez, Luis Hernández:
VCO-based Feature Extraction Architecture for Low Power Speech Recognition Applications. MWSCAS 2019: 1175-1178 - 2018
- [j10]Fernando Cardes, Eric Gutierrez, Andrés Quintero, Cesare Buffa, Andreas Wiesbauer, Luis Hernández:
0.04-mm2 103-dB-A Dynamic Range Second-Order VCO-Based Audio ΣΔ ADC in 0.13-µm CMOS. IEEE J. Solid State Circuits 53(6): 1731-1742 (2018) - [j9]Fernando Cardes, Andrés Quintero, Eric Gutierrez, Cesare Buffa, Andreas Wiesbauer, Luis Hernández:
SNDR Limits of Oscillator-Based Sensor Readout Circuits. Sensors 18(2): 445 (2018) - [j8]Eric Gutierrez, Luis Hernández, Fernando Cardes, Pieter Rombouts:
A Pulse Frequency Modulation Interpretation of VCOs Enabling VCO-ADC Architectures With Extended Noise Shaping. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(2): 444-457 (2018) - [c40]Eric Gutierrez, Pieter Rombouts, Luis Hernández:
Why and How VCO-based ADCs can improve instrumentation applications. ICECS 2018: 101-104 - [c39]Leidy Mabel Alvero-Gonzalez, Eric Gutierrez, Luis Hernández:
A Highly Linear Ring Oscillator for VCO-based ADCs in 65-nm CMOS. ICECS 2018: 465-468 - [c38]Eric Gutierrez, Luis Hernández, Susana Patón, Pieter Rombouts:
Optimal NTF zero placement in MASH VCO-ADCs with higher order noise shaping. ICECS 2018: 805-808 - [c37]Luis Hernández, Enrique Prefasi, Susana Patón, Eric Gutierrez:
VCO-ADC Resolution Enhancement Using Maximum Length Sequences. ISCAS 2018: 1-4 - 2017
- [c36]Andrés Quintero, Carlos Perez, Eric Gutierrez, Luis Hernández, Susana Patón:
Noise-shaping time-interleaved ADC based on a single ring oscillator and a sampling array. MWSCAS 2017: 683-686 - 2016
- [c35]Luis Hernández, Eric Gutierrez, Fernando Cardes:
Frequency-encoded integrators applied to filtering and sigma-delta modulation. ISCAS 2016: 478-481 - 2015
- [j7]Luis Hernández, Eric Gutierrez:
Analytical Evaluation of VCO-ADC Quantization Noise Spectrum Using Pulse Frequency Modulation. IEEE Signal Process. Lett. 22(2): 249-253 (2015) - [c34]Eric Gutierrez, Luis Hernández:
Spectral analysis of multibit VCO-ADCs and PFM-ADCs with sinusoidal inputs. ISCAS 2015: 1258-1261 - [c33]Fernando Cardes, Ruzica Jevtic, Luis Hernández, Andreas Wiesbauer, Dietmar Sträußnigg, Richard Gaggl:
A MEMS microphone interface based on a CMOS LC oscillator and a digital sigma-delta modulator. ISCAS 2015: 2233-2236 - [c32]Juan A. Torreño, Susana Patón, Laura Conesa-Peraleja, Luis Hernández, Dietmar Straeussnigg:
A noise coupled ΣΔ architecture using a Non Uniform Quantizer. NORCAS 2015: 1-4 - 2014
- [c31]Enrique Prefasi, Eric Gutierrez, Luis Hernández, Susana Patón, Sergio Walter, Ulrich Gaier:
A 0.03mm2, 40nm CMOS 1.5GS/s all-digital complementary PWM-GRO. ICECS 2014: 116-119 - [c30]Eric Gutierrez, Luis Hernández, Ulrich Gaier, Sergio Walter, Liang Zou:
A digitally corrected ADC using a passive pulse frequency modulator. ICECS 2014: 654-657 - [c29]Fernando Cardes, Luis Hernández, Javier Escobar, Andreas Wiesbauer, Dietmar Straeussnigg, Richard Gaggl:
A time-encoding CMOS capacitive sensor readout circuit with flicker noise reduction. MWSCAS 2014: 390-393 - [c28]Eric Gutierrez, Luis Hernández, Ulrich Gaier, Sergio Walter, Liang Zou:
A low power and low distortion VCO based ADC using a pulse frequency modulator. MWSCAS 2014: 487-490 - 2013
- [c27]Luis Hernández, Enrique Prefasi, Susana Patón:
A distortion corrected passive RC noise shaping ADC for biomedical applications. ISCAS 2013: 590-593 - [c26]Juan A. Torreño, Susana Patón, Luis Hernández, Enrique Prefasi, M. Presicce, G. Paoli:
A multi-stage and time-based continuous time ΣΔ Architecture using a Gated Ring Oscillator. ISCAS 2013: 1043-1046 - 2012
- [c25]Luis Hernández, Enrique Prefasi, Susana Patón, Pieter Rombouts:
Analysis of VCO based noise shaping ADCs linearized by PWM modulation. ICECS 2012: 352-355 - 2011
- [j6]Enrique Prefasi, Susana Patón, Luis Hernández:
A 7 mW 20 MHz BW Time-Encoding Oversampling Converter Implemented in a 0.08 mm 2 65 nm CMOS Circuit. IEEE J. Solid State Circuits 46(7): 1562-1574 (2011) - [c24]Francesco Cannillo, Enrique Prefasi, Luis Hernández, Ernesto Pun, Refet Firat Yazicioglu, Chris Van Hoof:
1.4V 13μW 83dB DR CT-ΣΔ modulator with Dual-Slope quantizer and PWM DAC for biopotential signal acquisition. ESSCIRC 2011: 267-270 - 2010
- [c23]Enrique Prefasi, Susana Patón, Luis Hernández, Richard Gaggl, Andreas Wiesbauer, Joerg Hauptmann:
A 0.08 mm2, 7mW Time-Encoding Oversampling Converter with 10 bits and 20MHz BW in 65nm CMOS. ESSCIRC 2010: 430-433 - [c22]Luis Hernández, Jorge Fernández, Enrique Prefasi, Susana Patón:
A time encoded decimation filter for noise shaped power DACs. ISCAS 2010: 289-292 - [c21]Luis Hernández, Andreas Wiesbauer:
Exploiting time resolution in nanometre CMOS data converters. ISCAS 2010: 1069-1072 - [c20]Susana Patón, Juan A. Torreño, Enrique Prefasi, Luis Hernández:
Continuous Time Cascade Sigma Delta Modulator without digital cancellation filters. ISCAS 2010: 4009-4012
2000 – 2009
- 2009
- [j5]Enrique Prefasi, Luis Hernández, Susana Patón, Andreas Wiesbauer, Richard Gaggl, Ernesto Pun:
A 0.1 mm2, Wide Bandwidth Continuous-Time ΔΣ ADC Based on a Time Encoding Quantizer in 0.13 µm CMOS. IEEE J. Solid State Circuits 44(10): 2745-2754 (2009) - [j4]Luis Hernández, Enrique Prefasi, Ernesto Pun, Susana Patón:
A 1.2-MHz 10-bit Continuous-Time Sigma-Delta ADC Using a Time Encoding Quantizer. IEEE Trans. Circuits Syst. II Express Briefs 56-II(1): 16-20 (2009) - [c19]Enrique Prefasi, Ernesto Pun, Luis Hernández, Susana Patón:
Second-order multi-bit ΣΔ ADC using a Pulse-Width Modulated DAC and an integrating quantizer. ICECS 2009: 37-40 - 2008
- [j3]Luis Hernández, Enrique Prefasi:
Analog-to-Digital Conversion Using Noise Shaping and Time Encoding. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7): 2026-2037 (2008) - [c18]Luis Hernández, Susana Patón:
Resolution enhancement of sigma-delta modulators using a tracking digital filter. ICECS 2008: 1111-1114 - [c17]Enrique Prefasi, Stijn Reekmans, Luis Hernández:
A one-path quadrature bandpass ΣΔ modulator based on distributed resonators at 25 MHz IF. ICECS 2008: 1123-1126 - [c16]Luis Hernández, Susana Patón, Enrique Prefasi:
An A/D converter based on pulse width modulation and the walsh-hadamard transform. ICECS 2008: 1217-1220 - [c15]Luis Hernández, Enrique Prefasi:
A subsampling bandpass SigmaDelta modulator with lumped and distributed resonators. ISCAS 2008: 1652-1655 - 2007
- [j2]Stijn Reekmans, Luis Hernández, Enrique Prefasi:
A Subsampling Quadrature Σ∆ Modulator Based on Distributed Resonators for Use in Radio Receiver. IEEE Trans. Circuits Syst. II Express Briefs 54-II(9): 820-824 (2007) - 2006
- [c14]Susana Patón, Manuel Sanchez-Renedo, Luis Hernández, Enrique Prefasi, Andreas Wiesbauer, Antonio Di Giandomenico, David San Segundo:
Design of Cascaded Continuous-Time Sigma-Delta Modulators. ICECS 2006: 50-53 - [c13]Luis Hernández, Enrique Prefasi:
Analog to digital conversion using a Pulse Width Modulator and an irregular sampling decoder. ICECS 2006: 716-719 - [c12]Manuel Sanchez-Renedo, Susana Patón, Luis Hernández:
A 2-2 Discrete Time Cascaded ΣΔ Modulator With NTF Zero Using Interstage Feedback. ICECS 2006: 954-957 - [c11]Luis Hernández, Enrique Prefasi, Pieter Rombouts:
A continuous-time band-pass Sigma Delta modulator implemented in 0.35µm BiCMOS using transmission lines. ISCAS 2006 - [c10]Luis Hernández, Susana Patón, Andreas Wiesbauer:
Spectral shaping of clock jitter errors for continuous time sigma-delta modulators. ISCAS 2006 - [c9]Andreas Wiesbauer, Dietmar Sträußnigg, Richard Gaggl, Martin Clara, Luis Hernández, Daniel Gruber:
Clock jitter compensation for current steering DACs. ISCAS 2006 - 2005
- [c8]Luis Hernández, Enrique Prefasi, Susana Patón, Pieter Rombouts:
Synthesis of sigma delta modulators employing continuous time delays. ISCAS (4) 2005: 4070-4073 - 2004
- [j1]Susana Patón, Antonio Di Giandomenico, Luis Hernández, Andreas Wiesbauer, Thomas Pötscher, Martin Clara:
A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution. IEEE J. Solid State Circuits 39(7): 1056-1063 (2004) - [c7]Susana Patón, Thomas Pötscher, Antonio Di Giandomenico, Klaus Kolhaupt, Luis Hernández, Andreas Wiesbauer, Martin Clara, Ramon Frutos:
Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators. CICC 2004: 527-530 - [c6]Luis Hernández, Pieter Rombouts, Enrique Prefasi, Susana Patón, Mario Garcia, Celia López:
A jitter insensitive continuous-time ΣΔ modulator using transmission lines. ICECS 2004: 109-112 - [c5]Luis Hernández, Andreas Wiesbauer, Susana Patón, Antonio Di Giandomenico:
Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction. ISCAS (1) 2004: 1072-1075 - 2003
- [c4]Antonio Di Giandomenico, Susana Patón, Andreas Wiesbauer, Luis Hernández, Thomas Pötscher, Lukas Dörrer:
A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13μm CMOS. ESSCIRC 2003: 233-236 - [c3]Luis Hernández, Susana Patón:
Continuous time sigma-delta modulators with transmission line resonators and improved jitter and excess loop delay performance. ISCAS (1) 2003: 989-992 - 2002
- [c2]Luis Hernández, Susana Patón:
A superregenerative receiver for phase and frequency modulated carriers. ISCAS (3) 2002: 81-84
1990 – 1999
- 1999
- [c1]Luis Hernández, Susana Patón:
A continuous-time noise-shaping modulator for logarithmic A/D conversion. ISCAS (2) 1999: 364-367
Coauthor Index
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