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2020 – today
- 2024
[j50]Yosuke Ueno
, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura:
Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines. IEEE Comput. Archit. Lett. 23(1): 6-9 (2024)- [c128]Satoshi Okada, Houda Jmila, Kunio Akashi, Takuho Mitsunaga, Yuji Sekiya, Hideki Takase, Gregory Blanc, Hiroshi Nakamura:
XAI-driven Adversarial Attacks on Network Intrusion Detectors. EICC 2024: 65-73 - [c127]Ai Nozaki, Takuya Kojima, Hiroshi Nakamura, Hideki Takase:
MLIR-Based Homomorphic Encryption Compiler for GPU. HEART 2024: 130-132 - [c126]Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura:
A Scalable Mapping Method for Elastic CGRAs. IPDPS (Workshops) 2024: 650-657 - [i4]Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura:
SFQ counter-based precomputation for large-scale cryogenic VQE machines. CoRR abs/2403.00363 (2024) - [i3]Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura:
C3-VQA: Cryogenic Counter-based Co-processor for Variational Quantum Algorithms. CoRR abs/2409.07847 (2024) - 2023
- [j49]Siyi Hu, Makiko Ito, Takahide Yoshikawa, Yuan He, Hiroshi Nakamura, Masaaki Kondo:
Adaptive Lossy Data Compression Extended Architecture for Memory Bandwidth Conservation in SpMV. IEICE Trans. Inf. Syst. 106(12): 2015-2025 (2023) - [j48]Satoshi Okada, Kunio Akashi, Daisuke Miyamoto, Yuji Sekiya, Hideki Takase, Hiroshi Nakamura:
Memory-saving LDoS Attacker Detection Algorithms in Zigbee Network. J. Inf. Process. 31: 537-549 (2023) - [j47]Siyi Hu, Masaaki Kondo, Yuan He, Ryuichi Sakamoto, Hao Zhang, Jun Zhou, Hiroshi Nakamura:
An edge re-ordering based acceleration architecture for improving data locality in graph analytics applications. Microprocess. Microsystems 102: 104895 (2023) - [c125]Yusuke Kanamori, Yusuke Yamasaki, Shintaro Hosoai, Hiroshi Nakamura, Hideki Takase:
An asynchronous federated learning focusing on updated models for decentralized systems with a practical framework. COMPSAC 2023: 1147-1154 - [c124]Kaito Kutsuna, Takuya Kojima, Hideki Takase, Hiroshi Nakamura:
An Area-Efficient Coarse-Grained Reconfigurable Array Design for Approximate Computing. MCSoC 2023: 59-64 - [c123]Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura:
ILP Based Mapping for Elastic CGRAs. RTCSA 2023: 281-282 - [i2]Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura:
Inter-temperature Bandwidth Reduction in Cryogenic QAOA Machines. CoRR abs/2310.01630 (2023) - 2022
- [c122]Toyotaro Suzumura, Akiyoshi Sugiki, Hiroyuki Takizawa, Akira Imakura, Hiroshi Nakamura, Kenjiro Taura, Tomohiro Kudoh, Toshihiro Hanawa, Yuji Sekiya, Hill Hiroki Kobayashi, Yohei Kuga, Ryo Nakamura, Renhe Jiang, Junya Kawase, Masatoshi Hanai, Hiroshi Miyazaki, Tsutomu Ishizaki, Daisuké Shimotoku, Daisuke Miyamoto, Kento Aida, Atsuko Takefusa, Takashi Kurimoto, Koji Sasayama, Naoya Kitagawa, Ikki Fujiwara, Yusuke Tanimura, Takayuki Aoki, Toshio Endo, Satoshi Ohshima, Keiichiro Fukazawa, Susumu Date, Toshihiro Uchibayashi:
mdx: A Cloud Platform for Supporting Data Science and Cross-Disciplinary Research Collaborations. DASC/PiCom/CBDCom/CyberSciTech 2022: 1-7 - [c121]Kiyotaka Hayami, Daichi Kawamoto, Mitsuru Shinagawa, Masayuki Makino, Hiroshi Nakamura, Naoyuki Honma:
Improvement of Signal Power in Intrabody Communication Using an Impedance Adjustment Circuit. GCCE 2022: 25-29 - [c120]Siyi Hu, Masaaki Kondo, Yuan He, Ryuichi Sakamoto, Hao Zhang, Jun Zhou, Hiroshi Nakamura:
GraphDEAR: An Accelerator Architecture for Exploiting Cache Locality in Graph Analytics Applications. PDP 2022: 135-143 - [i1]Toyotaro Suzumura, Akiyoshi Sugiki, Hiroyuki Takizawa, Akira Imakura, Hiroshi Nakamura, Kenjiro Taura, Tomohiro Kudoh, Toshihiro Hanawa, Yuji Sekiya, Hill Hiroki Kobayashi, Shin Matsushima, Yohei Kuga, Ryo Nakamura, Renhe Jiang, Junya Kawase, Masatoshi Hanai, Hiroshi Miyazaki, Tsutomu Ishizaki, Daisuké Shimotoku, Daisuke Miyamoto, Kento Aida, Atsuko Takefusa, Takashi Kurimoto, Koji Sasayama, Naoya Kitagawa, Ikki Fujiwara, Yusuke Tanimura, Takayuki Aoki, Toshio Endo, Satoshi Ohshima, Keiichiro Fukazawa, Susumu Date, Toshihiro Uchibayashi:
mdx: A Cloud Platform for Supporting Data Science and Cross-Disciplinary Research Collaborations. CoRR abs/2203.14188 (2022) - 2021
- [c119]Yuta Suzuki, Ryuichi Sakamoto, Hiroshi Nakamura:
Dynamic Power Management for 5G Small Cell Base Station. COMSNETS 2021: 492-500 - [c118]Satoshi Okada, Daisuke Miyamoto, Yuji Sekiya, Hideki Takase, Hiroshi Nakamura:
LDoS Attacker Detection Algorithms in Zigbee Network. iThings/GreenCom/CPSCom/SmartData/Cybermatics 2021: 43-50 - [c117]Shaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura:
Multi-objective Reinforcement Learning for Energy Harvesting Wireless Sensor Nodes. MCSoC 2021: 98-105 - [c116]Satoshi Okada, Daisuke Miyamoto, Yuji Sekiya, Hiroshi Nakamura:
New LDoS Attack in Zigbee Network and its Possible Countermeasures. SMARTCOMP 2021: 246-251 - 2020
- [j46]Takashi Nakada, Hiroyuki Yanagihashi, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura:
An Energy-Efficient Task Scheduling for Near Real-Time Systems on Heterogeneous Multicore Processors. IEICE Trans. Inf. Syst. 103-D(2): 329-338 (2020) - [j45]Noboru Shibata, Takahisa Kawabe, Taira Shibuya, Mario Sako, Kosuke Yanagidaira, Toshifumi Hashimoto, Hiroki Date, Manabu Sato, Tomoki Nakagawa, Junji Musha, Takatoshi Minamoto, Kazushige Kanda, Mizuki Uda, Dai Nakamura, Katsuaki Sakurai, Takahiro Yamashita, Jieyun Zhou, Ryoichi Tachibana, Teruo Takagiwa, Takahiro Sugimoto, Masatsugu Ogawa, Yusuke Ochi, Takahiro Shimizu, Kazuaki Kawaguchi, Masatsugu Kojima, Takeshi Ogawa, Tomoharu Hashiguchi, Ryo Fukuda, Masami Masuda, Koichi Kawakami, Tadashi Someya, Yasuyuki Kajitani, Yuuki Matsumoto, Jun Nakai, Jumpei Sato, Namasivayam Raghunathan, Yee Lih Koh, Shuo Chen, Juan Lee, Hiroaki Nasu, Hiroshi Sugawara, Koji Hosono, Toshiki Hisada, Hiroshi Nakamura, Osamu Nagao, Naoki Kobayashi, Makoto Miakashi, Yasushi Nagadomi, Tomoaki Nakano:
A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology. IEEE J. Solid State Circuits 55(1): 178-188 (2020) - [c115]Naoya Takahashi, Yoshiki Matsui, Sotaro Sawa, Daichi Kawamoto, Mitsuru Shinagawa, Kohei Hamamura, Hiroshi Nakamura, Naohiro Shimizu, Masaya Sugino:
Electric Field Communication using a Wide Metal Plate as the Transmission Path. GCCE 2020: 735-738 - [c114]Tomoya Yamashita, Daisuke Miyamoto, Yuji Sekiya, Hiroshi Nakamura:
Slow Scan Attack Detection Based on Communication Behavior. ICCNS 2020: 14-20
2010 – 2019
- 2019
- [c113]Kaede Torii, Shota Nakashima, Hiroshi Nakamura, Tetsuo Ooyagi, Kanya Tanaka, Hiroyuki Yagami:
Distinction of Heart Sound and Respiratory Sound Using Body Conduction Sound Sensor Based on HPSS. ACIT 2019: 31:1-31:6 - [c112]Shaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura:
Power Management of Wireless Sensor Nodes with Coordinated Distributed Reinforcement Learning. ICCD 2019: 638-647 - [c111]Yoshiki Matsui, Kenta Nezu, Naoya Takahashi, Koki Yoshioka, Mitsuru Shinagawa, Kohei Hamamura, Hiroshi Nakamura, Naohiro Shimizu:
Electric Field Communication using a Car Body as a Transmission Medium. ICST 2019: 1-5 - [c110]Noboru Shibata, Kazushige Kanda, Takahiro Shimizu, Jun Nakai, Osamu Nagao, Naoki Kobayashi, Makoto Miakashi, Yasushi Nagadomi, Takeshi Nakano, Takahisa Kawabe, Taira Shibuya, Mario Sako, Kosuke Yanagidaira, Toshifumi Hashimoto, Hiroki Date, Manabu Sato, Tomoki Nakagawa, H. Takamoto, Junji Musha, Takatoshi Minamoto, Mizuki Uda, Dai Nakamura, Katsuaki Sakurai, Takahiro Yamashita, Jieyun Zhou, Ryoichi Tachibana, Teruo Takagiwa, Takahiro Sugimoto, Mikio Ogawa, Yusuke Ochi, Kazuaki Kawaguchi, Masatsugu Kojima, Takeshi Ogawa, Tomoharu Hashiguchi, Ryo Fukuda, Masami Masuda, Koichi Kawakami, Tadashi Someya, Yasuyuki Kajitani, Yuuki Matsumoto, Naohito Morozumi, Jumpei Sato, Namas Raghunathan, Yee Lih Koh, Shuo Chen, Juan Lee, Hiroaki Nasu, Hiroshi Sugawara, Koji Hosono, Toshiki Hisada, T. Kaneko, Hiroshi Nakamura:
A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology. ISSCC 2019: 210-212 - [c109]Chang Hua Siau, Kwang-Ho Kim, Seungpil Lee, Katsuaki Isobe, Noboru Shibata, Kapil Verma, Takuya Ariki, Jason Li, Jong Yuh, Anirudh Amarnath, Qui Nguyen, Ohwon Kwon, Stanley Jeong, Heguang Li, Hua-Ling Hsu, Taiyuan Tseng, Steve Choi, Siddhesh Darne, Pradeep Anantula, Alex Yap, Hardwell Chibvongodze, Hitoshi Miwa, Minoru Yamashita, Mitsuyuki Watanabe, Koichiro Hayashi, Yosuke Kato, Toru Miwa, Jang Yong Kang, Masatoshi Okumura, Naoki Ookuma, Muralikrishna Balaga, Venky Ramachandra, Aki Matsuda, Swaroop Kulkarni, Raghavendra Rachineni, Pai K. Manjunath, Masahito Takehara, Anil Pai, Srinivas Rajendra, Toshiki Hisada, Ryo Fukuda, Naoya Tokiwa, Kazuaki Kawaguchi, Masashi Yamaoka, Hiromitsu Komai, Takatoshi Minamoto, Masaki Unno, Susumu Ozawa, Hiroshi Nakamura, Tomoo Hishida, Yasuyuki Kajitani, Lei Lin:
A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology. ISSCC 2019: 218-220 - 2018
- [c108]Hiroshi Maejima, Kazushige Kanda, Susumu Fujimura, Teruo Takagiwa, Susumu Ozawa, Jumpei Sato, Yoshihiko Shindo, Manabu Sato, Naoaki Kanagawa, Junji Musha, Satoshi Inoue, Katsuaki Sakurai, Naohito Morozumi, Ryo Fukuda, Yuui Shimizu, Toshifumi Hashimoto, Xu Li, Yuki Shimizu, Kenichi Abe, Tadashi Yasufuku, Takatoshi Minamoto, Hiroshi Yoshihara, Takahiro Yamashita, Kazuhiko Satou, Takahiro Sugimoto, Fumihiro Kono, Mitsuhiro Abe, Tomoharu Hashiguchi, Masatsugu Kojima, Yasuhiro Suematsu, Takahiro Shimizu, Akihiro Imamoto, Naoki Kobayashi, Makoto Miakashi, Kouichirou Yamaguchi, Sanad Bushnaq, Hicham Haibi, Masatsugu Ogawa, Yusuke Ochi, Kenro Kubota, Taichi Wakui, Dong He, Weihan Wang, Hiroe Minagawa, Tomoko Nishiuchi, Hao Nguyen, Kwang-Ho Kim, Ken Cheah, Yee Lih Koh, Feng Lu, Venky Ramachandra, Srinivas Rajendra, Steve Choi, Keyur Payak, Namas Raghunathan, Spiros Georgakis, Hiroshi Sugawara, Seungpil Lee, Takuya Futatsuyama, Koji Hosono, Noboru Shibata, Toshiki Hisada, Tetsuya Kaneko, Hiroshi Nakamura:
A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology. ISSCC 2018: 336-338 - 2017
- [j44]Takashi Nakada, Tomoki Hatanaka, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura:
An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation. IEICE Trans. Inf. Syst. 100-D(10): 2493-2504 (2017) - [j43]Hiroshi Nakamura, Masaru Nakano:
Scenario Analysis for Clean Energy Vehicles in UK Considering Introduction of Renewable Energy Sources. Int. J. Autom. Technol. 11(4): 592-600 (2017) - [j42]Shaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura:
Adaptive Power Management in Solar Energy Harvesting Sensor Node Using Reinforcement Learning. ACM Trans. Embed. Comput. Syst. 16(5s): 181:1-181:21 (2017) - [c107]Muhammad Khairul Nizar Bin Khairuddin, Kazuhiro Nakamoto, Hiroshi Nakamura, Kanya Tanaka, Shota Nakashima:
Heart Rate and Heart Rate Variability Measuring System by Using Smartphone. ACIT/CSII/BCD 2017: 47-52 - [c106]Toshimasa Miyazaki, Naoki Kamiya, Hiroshi Nakamura, Yuki Yokokura, Kiyoshi Ohishi:
Dual notch-type high-order frinction-free force observers for force sensorless fine force control. IECON 2017: 6715-6720 - [c105]Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki:
Building block multi-chip systems using inductive coupling through chip interface. ISOCC 2017: 152-154 - [c104]Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano:
Scalable deep neural network accelerator cores with cubic integration using through chip interface. ISOCC 2017: 155-156 - [c103]Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano:
The Design and Implementation of Scalable Deep Neural Network Accelerator Cores. MCSoC 2017: 13-20 - [c102]Takashi Nakada, Hiroyuki Yanagihashi, Hiroshi Nakamura, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi:
Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors. VLSI-SoC 2017: 1-6 - 2016
- [j41]Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki:
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. IEICE Trans. Electron. 99-C(8): 926-935 (2016) - [j40]Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura:
A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip. IEICE Trans. Inf. Syst. 99-D(12): 2881-2890 (2016) - [c101]Hiroshi Nakamura, Kiyoshi Ohishi, Yuki Yokokura, Toshimasa Miyazaki, Akifumi Tsukamoto:
Fine force control without force sensor based on reaction force estimation system considering static friction and kinetic friction. IECON 2016: 5076-5081 - [c100]Takashi Nakada, Hiroshi Nakamura, Toshifumi Nakamoto, Toru Shimizu:
Normally-off power management for sensor nodes of global navigation satellite system. ISOCC 2016: 193-194 - [c99]Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura:
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. ISSCC 2016: 132-133 - [c98]Takashi Nakada, Tomoki Hatanaka, Hiroshi Nakamura, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu:
An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis. VLSI-SoC 2016: 1-7 - 2015
- [j39]Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki:
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units. IEICE Trans. Electron. 98-C(7): 559-568 (2015) - [c97]Hiroshi Nakamura, Satoshi Ono:
Suggestion-based interactive video digest design by user-system cooperative evolution. CEC 2015: 2207-2214 - [c96]Takashi Nakada, Hiroyuki Yanagihashi, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura:
Energy-Efficient Continuous Task Scheduling for Near Real-Time Periodic Tasks. DSDIS 2015: 675-681 - [c95]Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura:
Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches. ICCD 2015: 149-156 - [c94]Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura:
Runtime multi-optimizations for energy efficient on-chip interconnections1. ICCD 2015: 455-458 - [c93]Yoshiyasu Takase, Hiroshi Nakamura, Minoru Koga, Toru Shikayama, Akihito Toyota:
Position sensorless control with accelerometer for linear and curvilinear synchronous motor. IECON 2015: 2378-2383 - [c92]Shinobu Miwa, Hiroshi Nakamura:
Profile-based power shifting in interconnection networks with on/off links. SC 2015: 37:1-37:11 - 2014
- [j38]Shinobu Miwa, Takara Inoue, Hiroshi Nakamura:
Area-Efficient Microarchitecture for Reinforcement of Turbo Mode. IEICE Trans. Inf. Syst. 97-D(5): 1196-1210 (2014) - [j37]Shinobu Miwa, Sho Aita, Hiroshi Nakamura:
Performance estimation of high performance computing systems with Energy Efficient Ethernet technology. Comput. Sci. Res. Dev. 29(3-4): 161-169 (2014) - [j36]Takashi Nakada, Kazuya Okamoto, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura:
Design Aid of Multi-core Embedded Systems with Energy Model. Inf. Media Technol. 9(4): 419-428 (2014) - [c91]Masaki Higashino, Hiroshi Fujimoto, Yoshiyasu Takase, Hiroshi Nakamura:
Step climbing control of wheeled robot based on slip ratio taking account of work load shift by anti-dive force of suspensions and accerelation. AMC 2014: 167-172 - [c90]Hiroshi Nakamura, Takashi Nakada, Shinobu Miwa:
Normally-off computing project: Challenges and opportunities. ASP-DAC 2014: 1-5 - [c89]Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. ASP-DAC 2014: 843-848 - [c88]Masaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura:
Design and evaluation of fine-grained power-gating for embedded microprocessors. DATE 2014: 1-6 - [c87]Yoshiyasu Takase, Hiroshi Nakamura, Takashi Mamba, Fei Zhao:
Proposal of position sensorless control and torque ripple compensation based on torque sensor feedback. IECON 2014: 805-810 - [c86]Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. ISSoC 2014: 1-7 - [c85]Takashi Nakada, Takuya Shigematsu, Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu:
Data-aware power management for periodic real-time systems with non-volatile memory. NVMSA 2014: 1-6 - [c84]Hiroshi Nakamura, Satoshi Ono:
Video summarization support by Interactive Evolutionary Computation. SCIS&ISIS 2014: 48-53 - 2013
- [j35]Yuetsu Kodama, Satoshi Itoh, Toshiyuki Shimizu, Satoshi Sekiguchi, Hiroshi Nakamura, Naohiko Mori:
Imbalance of CPU temperatures in a blade system and its impact for power consumption of fans. Clust. Comput. 16(1): 27-37 (2013) - [j34]Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki:
Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. IEICE Trans. Electron. 96-C(4): 404-412 (2013) - [j33]Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro 33(6): 6-15 (2013) - [c83]Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura:
McRouter: Multicast within a router for high performance network-on-chips. PACT 2013: 319-329 - [c82]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips 2013: 1-3 - [c81]Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura:
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. DATE 2013: 1813-1818 - [c80]Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL 2013: 1 - [c79]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium 2013: 1 - [c78]Toshiya Komoda, Shingo Hayashi, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura:
Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping. ICCD 2013: 349-356 - [c77]Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Naoya Maruyama:
Integrating Multi-GPU Execution in an OpenACC Compiler. ICPP 2013: 260-269 - [c76]Masaki Higashino, Hiroshi Fujimoto, Yoshiyasu Takase, Hiroshi Nakamura:
Proposal of step climbing of wheeled robot using slip ratio control. IECON 2013: 6545-6550 - [c75]Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura:
Predict-More Router: A Low Latency NoC Router with More Route Predictions. IPDPS Workshops 2013: 842-850 - [c74]Takashi Nakada, Shinobu Miwa, Keisuke Y. Yano, Hiroshi Nakamura:
Performance modeling for designing NoC-based multiprocessors. RSP 2013: 30-36 - 2012
- [j32]Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura:
Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2301-2308 (2012) - [j31]Yuan He, Hiroki Matsutani, Hiroshi Sasaki, Hiroshi Nakamura:
Adaptive Data Compression on 3D Network-on-Chips. Inf. Media Technol. 7(1): 153-160 (2012) - [c73]Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, Hiroshi Nakamura:
Scalability-based manycore partitioning. PACT 2012: 107-116 - [c72]Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano:
A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. ASP-DAC 2012: 407-412 - [c71]Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL 2012: 543-546 - [c70]Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT 2012: 293-296 - [c69]Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura:
A novel power-gating scheme utilizing data retentiveness on caches. ACM Great Lakes Symposium on VLSI 2012: 91-94 - [c68]Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura:
Stepwise sleep depth control for run-time leakage power saving. ACM Great Lakes Symposium on VLSI 2012: 233-238 - [c67]Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura:
Communication Library to Overlap Computation and Communication for OpenCL Application. IPDPS Workshops 2012: 567-573 - [c66]Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura:
Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating. ISQED 2012: 625-632 - [r1]Hiroshi Sasaki, Hideharu Amano, Kimiyoshi Usami, Masaaki Kondo, Mitaro Namiki, Hiroshi Nakamura:
Geyser. Handbook of Energy-Aware and Green Computing 2012: 49-65 - 2011
- [j30]Seidai Takeda, Kyundong Kim, Hiroshi Nakamura, Kimiyoshi Usami:
Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2499-2509 (2011) - [j29]Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano:
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. Inf. Media Technol. 6(4): 1092-1102 (2011) - [j28]Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano:
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. IPSJ Trans. Syst. LSI Des. Methodol. 4: 182-192 (2011) - [j27]Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo:
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro 31(6): 6-18 (2011) - [j26]Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano:
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4): 520-533 (2011) - [c65]Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo:
Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC 2011: 87-88 - [c64]Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura, Masaaki Kondo:
SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. COOL Chips 2011: 1-3 - [c63]Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo:
Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT 2011: 1-8 - [c62]Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura:
On-chip detection methodology for break-even time of power gated function units. ISLPED 2011: 241-246 - [p1]Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano:
Run-Time Power-Gating Techniques for Low-Power On-Chip Networks. Low Power Networks-on-Chip 2011: 21-43 - [e2]Naehyuck Chang, Hiroshi Nakamura, Koji Inoue, Kenichi Osada, Massimo Poncino:
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011. IEEE/ACM 2011, ISBN 978-1-61284-660-6 [contents] - 2010
- [c61]Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo:
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. ASP-DAC 2010: 369-370 - [c60]Yuetsu Kodama, Satoshi Itoh, Toshiyuki Shimizu, Satoshi Sekiguchi, Hiroshi Nakamura, Naohiko Mori:
Power Reduction Scheme of Fans in a Blade System by Considering the Imbalance of CPU Temperatures. GreenCom/CPSCom 2010: 81-87 - [c59]Satoshi Itoh, Yuetsu Kodama, Hiroshi Shimizu, Satoshi Sekiguchi, Hiroshi Nakamura, Naohiko Mori:
Power consumption and efficiency of cooling in a Data Center. GRID 2010: 305-312 - [c58]Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Adaptive power gating for function units in a microprocessor. ISQED 2010: 29-37 - [c57]Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano:
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. NOCS 2010: 61-68 - [e1]Yutaka Ishikawa, Dong Tang, Hiroshi Nakamura:
16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010, Tokyo, Japan, December 13-15, 2010. IEEE Computer Society 2010, ISBN 978-1-4244-8975-6 [contents]
2000 – 2009
- 2009
- [j25]Takeshi Mishima, Hiroshi Nakamura:
Pangea: An Eager Database Replication Middleware guaranteeing Snapshot Isolation without Modification of Database Servers. Proc. VLDB Endow. 2(1): 1066-1077 (2009) - [j24]Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura:
Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping. IEEE Trans. Very Large Scale Integr. Syst. 17(6): 848-852 (2009) - [c56]Hiroshi Sasaki, Takatsugu Oya, Masaaki Kondo, Hiroshi Nakamura:
Power-performance modeling of heterogeneous cluster-based web servers. GRID 2009: 225-231 - [c55]Noriko Takagi, Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura:
Cooperative shared resource access control for low-power chip multiprocessors. ISLPED 2009: 177-182 - [c54]Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura:
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design 2009: 381-386 - 2008
- [c53]Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
A fine-grain dynamic sleep control scheme in MIPS R3000. ICCD 2008: 612-617 - [c52]Bogdan Tomoyuki Nassu, Takashi Nanya, Hiroshi Nakamura:
Discovering Implicit Redundancies in Network Communications for Detecting Inconsistent Values. ICDM Workshops 2008: 144-153 - [c51]Bogdan Tomoyuki Nassu, Takashi Nanya, Hiroshi Nakamura:
Detecting Inconsistent Values Caused by Interaction Faults Using Automatically Located Implicit Redundancies. PRDC 2008: 138-145 - 2007
- [j23]Masaaki Kondo, Hiroshi Sasaki, Hiroshi Nakamura:
Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS. SIGARCH Comput. Archit. News 35(1): 31-38 (2007) - [c50]Hiroshi Sasaki, Yoshimichi Ikeda, Masaaki Kondo, Hiroshi Nakamura:
An intra-task dvfs technique based on statistical analysis of hardware events. Conf. Computing Frontiers 2007: 123-130 - [c49]Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya:
Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. DATE 2007: 797-802 - [c48]Hiroshi Nakamura:
Fast Abstracts. DSN 2007: 812 - [c47]Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya:
Power reduction of chip multi-processors using shared resource control cooperating with DVFS. ICCD 2007: 615-622 - [c46]Masaaki Kondo, Yoshimichi Ikeda, Hiroshi Nakamura:
A High Performance Cluster System Design by Adaptie Power Control. IPDPS 2007: 1-8 - [c45]Takeshi Mishima, Hiroshi Nakamura:
A Proposal of New Dependable Database Middleware with Consistency and Concurrency Control. PRDC 2007: 334-337 - 2006
- [j22]Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya:
Design Method of High Performance and Low Power Functional Units Considering Delay Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3519-3528 (2006) - [j21]Daisuke Komura, Kunihiro Nishimura, Shumpei Ishikawa, Binaya Panda, Jing Huang, Hiroshi Nakamura, Sigeo Ihara, Michitaka Hirose, Keith W. Jones, Hiroyuki Aburatani:
Noise Reduction from Genotyping Microarrays Using Probe Level Information. Silico Biol. 6(1-2): 79-92 (2006) - [c44]Taisuke Boku, Mitsuhisa Sato, Daisuke Takahashi, Hiroshi Nakashima, Hiroshi Nakamura, Satoshi Matsuoka, Yoshihiko Hotta:
MegaProto/E: power-aware high-performance cluster with commodity technology. IPDPS 2006 - [c43]Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura:
Energy-efficient dynamic instruction scheduling logic through instruction grouping. ISLPED 2006: 43-48 - [c42]Kohji Itoh, Hiroshi Nakamura, Shunsuke Unno, Jun'ichi Kakegawa:
A System Assisting Acquisition of Japanese Expressions Through Read-Write-Hear-Speaking and Comparing Between Use Cases of Relevant Expressions. KES (2) 2006: 1071-1078 - 2005
- [j20]Daisuke Komura, Hiroshi Nakamura, Shuichi Tsutsumi, Hiroyuki Aburatani, Sigeo Ihara:
Multidimensional support vector machines for visualization of gene expression data. Bioinform. 21(4): 439-444 (2005) - [c41]Ken-ichi Kurata, Hiroshi Nakamura, Vincent Breton:
Secret sequence comparison on public grid computing resources. CCGRID 2005: 832-839 - [c40]Masaaki Kondo, Hiroshi Nakamura:
A Small, Fast and Low-Power Register File by Bit-Partitioning. HPCA 2005: 40-49 - [c39]Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sato, Taisuke Boku, Satoshi Matsuoka, Daisuke Takahashi, Yoshihiko Hotta:
MegaProto: A Low-Power and Compact Cluster for High-Performance Computing. IPDPS 2005 - [c38]Chikafumi Takahashi, Mitsuhisa Sato, Daisuke Takahashi, Taisuke Boku, Hiroshi Nakamura, Masaaki Kondo, Motonobu Fujita:
Empirical Study for Optimization of Power-Performance with On-Chip Memory. ISHPC 2005: 466-479 - [c37]Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura:
Dynamic Instruction Cascading on GALS Microprocessors. PATMOS 2005: 30-39 - [c36]Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sato, Taisuke Boku, Satoshi Matsuoka, Daisuke Takahashi, Yoshihiko Hotta:
MegaProto: 1 TFlops/10kW Rack Is Feasible Even with Only Commodity Technology. SC 2005: 28 - 2004
- [j19]Nicolas Jacq, Christophe Blanchet, Christophe Combet, Emmanuel Cornillot, Laurent Duret, Ken-ichi Kurata, Hiroshi Nakamura, T. Silvestre, Vincent Breton:
Grid as a bioinformatic tool. Parallel Comput. 30(9-10): 1093-1107 (2004) - [c35]Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura:
Data Movement Optimization for Software-Controlled On-Chip Memory. Interaction between Compilers and Computer Architectures 2004: 120-127 - [c34]Ken-ichi Kurata, Vincent Breton, Hiroshi Nakamura:
Secret sequence comparison in distributed computing environments by interval sampling. CIBCB 2004: 198-205 - [c33]Masaaki Kondo, Hiroshi Nakamura:
Dynamic Processor Throttling for Power Efficient Computations. PACS 2004: 120-134 - [c32]Daisuke Komura, Hiroshi Nakamura, Shuichi Tsutsumi, Hiroyuki Aburatani, Sigeo Ihara:
Multidimensional support vector machines for visualization of gene expression data. SAC 2004: 175-179 - [c31]Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya:
Skewed Checkpointing for Tolerating Multi-Node Failures. SRDS 2004: 116-125 - [c30]Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, Daisuke Takahashi, Hiroshi Nakamura, Mitsuhisa Sato:
SCIMA-SMP: on-chip memory processor architecture for SMP. WMPI 2004: 121-128 - 2003
- [j18]Nattha Sretasereekul, Hiroshi Saito, Euiseok Kim, Metehan Özcan, Masashi Imai, Hiroshi Nakamura, Takashi Nanya:
Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3028-3037 (2003) - [c29]Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya:
Logic optimization for asynchronous speed independent controllers using transduction method. ASP-DAC 2003: 197-202 - [c28]Euiseok Kim, Dong-Ik Lee, Hiroshi Saito, Hiroshi Nakamura, Jeong-Gun Lee, Takashi Nanya:
Performance optimization of synchronous control units for datapaths with variable delay arithmetic units. ASP-DAC 2003: 816-819 - [c27]Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya:
Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. ASYNC 2003: 184-195 - [c26]Ken-ichi Kurata, Vincent Breton, Hiroshi Nakamura:
A Method to Find Uniq e Sequences on Distrib ted Genomic Databases. CCGRID 2003: 62-69 - [c25]Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, Takashi Nanya:
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units. DATE 2003: 10276-10281 - [c24]Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya:
A zero-time-overhead asynchronous four-phase controller. ISCAS (5) 2003: 205-208 - [c23]Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya:
Control signal sharing of asynchronous circuits using datapath delay information. ISCAS (5) 2003: 617-620 - 2002
- [j17]Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Hiroshi Nakamura:
Circuit techniques for a 1.8-V-only NAND flash memory. IEEE J. Solid State Circuits 37(1): 84-89 (2002) - [j16]Kenichi Imamiya, Hiroshi Nakamura, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian J. Che:
A 125-mm2 1-Gb NAND flash memory with 10-MByte/s program speed. IEEE J. Solid State Circuits 37(11): 1493-1501 (2002) - [j15]Masaaki Kondo, Motonobu Fujita, Hiroshi Nakamura:
Software-controlled on-chip memory for high-performance and low-power computing. SIGARCH Comput. Archit. News 30(3): 7-8 (2002) - [c22]T. Ohneda, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura:
Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. APCCAS (1) 2002: 211-216 - [c21]Masaaki Kondo, Mitsugu Iwamoto, Hiroshi Nakamura:
Cache Line Impact on 3D PDE Solvers. ISHPC 2002: 301-309 - [c20]Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya:
Logic Optimization for Asynchronous SI Controllers using Transduction Method. IWLS 2002: 245-250 - [c19]Ken-ichi Kurata, Christian Saguez, Gerald Dine, Hiroshi Nakamura:
Rapid Analysis of Specificity of PCR Product on the Whole Genome. PDPTA 2002: 246-252 - [c18]Hiroshi Nakamura, Takanori Arai, Masahiro Fujita:
Formal Verification of a Pipelined Processor with New Memory. PRDC 2002: 321-324 - 2001
- [c17]Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno:
Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. ASYNC 2001: 162-172 - [c16]Masahiro Fujita, Hiroshi Nakamura:
The standard SpecC language. ISSS 2001: 81-86 - 2000
- [j14]Daigoro Isobe, Hiroshi Nakamura, Ryuta Shimizu:
Real-time FEM Control System for Connected Piezoelectric Actuators. J. Robotics Mechatronics 12(2): 172-179 (2000) - [c15]Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, Taisuke Boku:
SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing. ICCD 2000: 105-111 - [c14]Hiroshi Nakamura, Masaaki Kondo, Taisuke Boku:
Software Controlled Reconfigurable On-Chip Memory for High Performance Computing. Intelligent Memory Systems 2000: 15-32
1990 – 1999
- 1999
- [j13]Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui:
A 130-mm/2, 256-Mbit NAND flash with shallow trench isolation technology. IEEE J. Solid State Circuits 34(11): 1536-1543 (1999) - [j12]Sinya Aoki, R. Burkhalter, Kazuyuki Kanaya, T. Yoshié, Taisuke Boku, Hiroshi Nakamura, Yoshiyuki Yamashita:
Performance of lattice QCD programs on CP-PACS. Parallel Comput. 25(10-11): 1243-1255 (1999) - [j11]Kisaburo Nakazawa, Hiroshi Nakamura, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita:
CP-PACS: A massively parallel processor at the University of Tsukuba. Parallel Comput. 25(13-14): 1635-1661 (1999) - [j10]Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau:
Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. IEEE Trans. Computers 48(2): 142-149 (1999) - 1998
- [j9]Hiroshi Nakamura, Hisakazu Tsuboya, Masatomo Nakano, Akihisa Nakajima:
Applying ATM to mobile infrastructure networks. IEEE Commun. Mag. 36(1): 66-73 (1998) - [j8]Huainan Ma, Sher Jiun Fang, Fujiang Lin, Khen-Sang Tan, Junichi Shibata, Atsushi Tamura, Hiroshi Nakamura:
A GaAs upconverter MMIC with an automatic gain control amplifier for 1.9 GHz PHS. IEEE J. Solid State Circuits 33(9): 1297-1305 (1998) - 1997
- [j7]Jin-Ki Kim, Koji Sakui, Sung-Soo Lee, Yasuo Itoh, Suk-Chon Kwon, Kazuhisa Kanazawa, Ki-Jun Lee, Hiroshi Nakamura, Kang-Young Kim, Toshihiko Himeno, Jang-Rae Kim, Kazushige Kanda, Tae-Sung Jung, Yoichi Oshima, Kang-Deog Suh, Kazuhiko Hashimoto, Sung-Tae Ahn, Junichi Miyamoto:
A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed. IEEE J. Solid State Circuits 32(5): 670-680 (1997) - [c13]Takayuki Morimoto, Kazushi Saito, Hiroshi Nakamura, Taisuke Boku, Kisaburo Nakazawa:
Advanced processor design using hardware description language AIDL. ASP-DAC 1997: 387-390 - [c12]Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau:
A Data Alignment Technique for Improving Cache Performance. ICCD 1997: 587-592 - [c11]Taisuke Boku, Ken'ichi Itakura, Hiroshi Nakamura, Kisaburo Nakazawa:
CP-PACS: A Massively Parallel Processor for Large Scale Scientific Calculations. International Conference on Supercomputing 1997: 108-115 - [c10]Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau:
Improving cache Performance Through Tiling and Data Alignment. IRREGULAR 1997: 167-185 - 1996
- [j6]Ken Takeuchi, Tomoharu Tanaka, Hiroshi Nakamura:
A double-level-Vth select gate array architecture for multilevel NAND flash memories. IEEE J. Solid State Circuits 31(4): 602-609 (1996) - [j5]Taisuke Boku, Kisaburo Nakazawa, Hiroshi Nakamura, Takeshi Sone, Takeshi Mishima, Ken'ichi Itakura:
Adaptive routing technique on hypercrossbar network and its evaluation. Syst. Comput. Jpn. 27(4): 55-64 (1996) - 1995
- [j4]Yoshihisa Iwata, Ken-ichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Hideko Oodaira, Masaki Momodomi, Yasuo Itoh, Toshiharu Watanabe, Hitoshi Araki, Kazuhito Narita, Kazunori Masuda, Junichi Miyamoto:
A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM. IEEE J. Solid State Circuits 30(11): 1157-1164 (1995) - 1994
- [j3]Tomoharu Tanaka, Yoshiyuki Tanaka, Hiroshi Nakamura, Koji Sakui, Hideko Oodaira, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka, Hisashi Hara:
A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory. IEEE J. Solid State Circuits 29(11): 1366-1373 (1994) - [c9]Hiroshi Nakamura, Kisaburo Nakazawa, Hang Li, Hiromitsu Imori, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita:
Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers. HICSS (1) 1994: 368-377 - 1993
- [c8]Hiroshi Nakamura, Taisuke Boku, Hideo Wada, Hiromitsu Imori, Ikuo Nakata, Yasuhiro Inagami, Kisaburo Nakazawa, Yoshiyuki Yamashita:
A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers. International Conference on Supercomputing 1993: 298-307 - 1992
- [c7]Kisaburo Nakazawa, Hiroshi Nakamura, Hiromitsu Imori, Shun Kawabe:
Pseudo Vector Processor Based on Register-Windowed Superscalar Pipeline. SC 1992: 642-651 - 1990
- [c6]Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka:
A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. CAV 1990: 76-85 - [c5]Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka:
A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. CAV (DIMACS/AMS volume) 1990: 493-504 - [c4]Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka:
Practical design assistance at register transfer level using a data path verifier. ICCD 1990: 99-102
1980 – 1989
- 1989
- [c3]Hiroshi Nakamura, Masaya Nakai, Shinji Kono, Masahiro Fujita, Hidehiko Tanaka:
Logic Design Assistence Using Temporal Logic Based Language Tokio. LP 1989: 174-183 - 1987
- [j2]Yoshimasa Daido, Sadao Takenaka, Eisuke Fukuda, Toshiaki Sakane, Hiroshi Nakamura:
Multilevel QAM Modulation Techniques for Digital Microwave Radios. IEEE J. Sel. Areas Commun. 5(3): 336-341 (1987) - 1986
- [j1]Yoshimasa Daido, Eisuke Fukuda, Yukio Takeda, Hiroshi Nakamura:
Theoretical Evalution of Signatures and CNR Penalties Caused by Modem Impairments in Multilevel QAM Digital Radio Modems. IEEE Trans. Commun. 34(7): 654-661 (1986) - 1985
- [c2]Masahiro Fujita, Makoto Ishisone, Hiroshi Nakamura, Hidehiko Tanaka, Tohru Moto-Oka:
Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis. LP 1985: 246-255 - 1984
- [c1]Sadao Takenaka, Yukio Takeda, Toshiaki Sakane, Hiroshi Nakamura, N. Toyonaga:
A New 4 GHz 90 Mbps Digital Radio System Using 64-QAM Modulation. ICC (2) 1984: 642-645
Coauthor Index
[j49] [j47] [c120] [c117] [c112] [j42] [c105] [c104] [c103] [j41] [j40] [j39] [c94] [c89] [c88] [c86] [j34] [j33] [c82] [c80] [c79] [c71] [c70] [r1] [j29] [j28] [j27] [c65] [c64] [c63] [c61] [c58] [j24] [c56] [c55] [c54] [c53] [j23] [c50] [c49] [c47] [c46] [j22] [c43] [c40] [c38] [c37] [c35] [c33] [c31] [c30] [j15] [c22] [c21] [c15] [c14]
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