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Zhaojun Wo Zhaojun Wo Israel Koren Synthesis of Saturating Counters Using Traditional and Non-Traditional Basic Counters. 114-121 2005 conf/arith/2005 IEEE Symposium on Computer Arithmetic https://doi.org/10.1109/ARITH.2005.42 https://doi.ieeecomputersociety.org/10.1109/ARITH.2005.42 db/conf/arith/arith2005.html#WoK05 Zhaojun Wo Israel Koren Effective analytical delay model for transistor sizing. 387-392 2005 conf/aspdac/2005 ASP-DAC https://doi.org/10.1145/1120725.1120882 https://doi.org/10.1109/ASPDAC.2005.1466194 db/conf/aspdac/aspdac2005.html#WoK05 Zhaojun Wo Israel Koren Maciej J. Ciesielski An ILP Formulation for Yield-driven Architectural Synthesis. 12-20 2005 conf/dft/2005 DFT https://doi.org/10.1109/DFTVS.2005.16 https://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.16 db/conf/dft/dft2005.html#WoKC05 Zhaojun Wo Israel Koren Maciej J. Ciesielski Yield-aware Floorplanning. 247-253 2005 conf/dsd/2005 DSD https://doi.org/10.1109/DSD.2005.80 https://doi.ieeecomputersociety.org/10.1109/DSD.2005.80 db/conf/dsd/dsd2005.html#WoKC05 Zhaojun Wo Israel Koren Technology Mapping for Reliability Enhancement in Logic Synthesis. 137-142 2005 conf/isqed/2005 ISQED https://doi.org/10.1109/ISQED.2005.118 https://doi.ieeecomputersociety.org/10.1109/ISQED.2005.118 db/conf/isqed/isqed2005.html#WoK05 Maciej J. Ciesielski Israel Koren