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Tomasz Madajczak

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2006
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Tomasz Madajczak, Henryk Krawczyk:
Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs. PARELEC 2006: 62-67
2005
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Tomasz Madajczak, Henryk Krawczyk:
Implementing Critical Sections with the Shared Explicit Cache System in the Shared Memory Parallel Architectures. PARCO 2005: 699-706
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Tomasz Madajczak:
Taking Advantage of the SHECS-Based Critical Sections in the Shared Memory Parallel Architectures. PPAM 2005: 26-33
2004
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Henryk Krawczyk, Tomasz Madajczak:
Optimal Programming of Critical Sections in Modern Network Processors under Performance Requirements. PARELEC 2004: 25-30
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Tomasz Madajczak:
An Optimal Abstraction Model for Hardware Multithreading in Modern Processor Architectures. PARELEC 2004: 71-76

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